transactor_sm Entity Reference

Inheritance diagram for transactor_sm:

Entities
rtl	architecture

Libraries
ieee
work

Use Clauses
std_logic_1164
numeric_std
ipbus	Package <ipbus>

Ports
clk	in std_logic
rst	in std_logic
rx_data	in std_logic_vector ( 31 downto 0 )
rx_ready	in std_logic
rx_next	out std_logic
tx_data	out std_logic_vector ( 31 downto 0 )
tx_we	out std_logic
tx_hdr	out std_logic
tx_err	out std_logic
ipb_out	out ipb_wbus
ipb_in	in ipb_rbus
cfg_we	out std_logic
cfg_addr	out std_logic_vector ( 1 downto 0 )
cfg_din	in std_logic_vector ( 31 downto 0 )
cfg_dout	out std_logic_vector ( 31 downto 0 )

Member Data Documentation

cfg_addr

cfg_addr out std_logic_vector ( 1 downto 0 )

Port

cfg_din

cfg_din in std_logic_vector ( 31 downto 0 )

Port

cfg_dout

cfg_dout out std_logic_vector ( 31 downto 0 )

Port

cfg_we

cfg_we out std_logic

Port

clk

clk in std_logic

Port

ieee

ieee

Library

ipb_in

ipb_in in ipb_rbus

Port

ipb_out

ipb_out out ipb_wbus

Port

ipbus

ipbus

Package

numeric_std

numeric_std

Package

rst

rst in std_logic

Port

rx_data

rx_data in std_logic_vector ( 31 downto 0 )

Port

rx_next

rx_next out std_logic

Port

rx_ready

rx_ready in std_logic

Port

std_logic_1164

std_logic_1164

Package

tx_data

tx_data out std_logic_vector ( 31 downto 0 )

Port

tx_err

tx_err out std_logic

Port

tx_hdr

tx_hdr out std_logic

Port

tx_we

tx_we out std_logic

Port

work

work

Library

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/transactor_sm.vhd