rtl Architecture Reference

Processes
PROCESS_46	( clk )
PROCESS_47	( clk )
PROCESS_48	( state , rx_data , ipb_in .ipb_err , timer , write )
PROCESS_61	( clk )
PROCESS_62	( clk )
PROCESS_63	( state , rx_data , ipb_in .ipb_err , timer , write )
PROCESS_598	( clk )
PROCESS_599	( clk )
PROCESS_600	( state , rx_data , ipb_in .ipb_err , timer , write )

Constants
TIMEOUT	integer := 255
TRANS_RD	std_logic_vector ( 3 downto 0 ) := X " 0 "
TRANS_WR	std_logic_vector ( 3 downto 0 ) := X " 1 "
TRANS_RDN	std_logic_vector ( 3 downto 0 ) := X " 2 "
TRANS_WRN	std_logic_vector ( 3 downto 0 ) := X " 3 "
TRANS_RMWB	std_logic_vector ( 3 downto 0 ) := X " 4 "
TRANS_RMWS	std_logic_vector ( 3 downto 0 ) := X " 5 "
TRANS_RD_CFG	std_logic_vector ( 3 downto 0 ) := X " 6 "
TRANS_WR_CFG	std_logic_vector ( 3 downto 0 ) := X " 7 "

Types
state_type	( ST_IDLE , ST_HDR , ST_ADDR , ST_BUS_CYCLE , ST_RMW_1 , ST_RMW_2 )

Signals
state	state_type
rx_ready_d	std_logic
start	std_logic
rmw_cyc	std_logic
cfg_cyc	std_logic
rmw_write	std_logic
write	std_logic
strobe	std_logic
ack	std_logic
last_wd	std_logic
trans_type	std_logic_vector ( 3 downto 0 )
addr	unsigned ( 31 downto 0 )
words_todo	unsigned ( 7 downto 0 )
words_done	unsigned ( 7 downto 0 )
timer	unsigned ( 7 downto 0 )
rmw_coeff	std_logic_vector ( 31 downto 0 )
rmw_input	std_logic_vector ( 31 downto 0 )
rmw_result	std_logic_vector ( 31 downto 0 )
data_out	std_logic_vector ( 31 downto 0 )
err	std_logic_vector ( 3 downto 0 )
err_d	std_logic_vector ( 3 downto 0 )
hdr	std_logic_vector ( 31 downto 0 )

Member Function Documentation

PROCESS_46()

PROCESS_46 (   clk   )

Process

PROCESS_47()

PROCESS_47 (   clk   )

Process

PROCESS_48()

PROCESS_48 (   state ,   rx_data ,   ipb_in .ipb_err ,   timer ,   write   )

Process

PROCESS_598()

PROCESS_598 (   clk   )

Process

PROCESS_599()

PROCESS_599 (   clk   )

Process

PROCESS_600()

PROCESS_600 (   state ,   rx_data ,   ipb_in .ipb_err ,   timer ,   write   )

Process

PROCESS_61()

PROCESS_61 (   clk   )

Process

PROCESS_62()

PROCESS_62 (   clk   )

Process

PROCESS_63()

PROCESS_63 (   state ,   rx_data ,   ipb_in .ipb_err ,   timer ,   write   )

Process

Member Data Documentation

ack

ack std_logic

Signal

addr

addr unsigned ( 31 downto 0 )

Signal

cfg_cyc

cfg_cyc std_logic

Signal

data_out

data_out std_logic_vector ( 31 downto 0 )

Signal

err

err std_logic_vector ( 3 downto 0 )

Signal

err_d

err_d std_logic_vector ( 3 downto 0 )

Signal

hdr

hdr std_logic_vector ( 31 downto 0 )

Signal

last_wd

last_wd std_logic

Signal

rmw_coeff

rmw_coeff std_logic_vector ( 31 downto 0 )

Signal

rmw_cyc

rmw_cyc std_logic

Signal

rmw_input

rmw_input std_logic_vector ( 31 downto 0 )

Signal

rmw_result

rmw_result std_logic_vector ( 31 downto 0 )

Signal

rmw_write

rmw_write std_logic

Signal

rx_ready_d

rx_ready_d std_logic

Signal

start

start std_logic

Signal

state

state state_type

Signal

state_type

state_type ( ST_IDLE , ST_HDR , ST_ADDR , ST_BUS_CYCLE , ST_RMW_1 , ST_RMW_2 )

Type

strobe

strobe std_logic

Signal

TIMEOUT

TIMEOUT integer := 255

Constant

timer

timer unsigned ( 7 downto 0 )

Signal

TRANS_RD

TRANS_RD std_logic_vector ( 3 downto 0 ) := X " 0 "

Constant

TRANS_RD_CFG

TRANS_RD_CFG std_logic_vector ( 3 downto 0 ) := X " 6 "

Constant

TRANS_RDN

TRANS_RDN std_logic_vector ( 3 downto 0 ) := X " 2 "

Constant

TRANS_RMWB

TRANS_RMWB std_logic_vector ( 3 downto 0 ) := X " 4 "

Constant

TRANS_RMWS

TRANS_RMWS std_logic_vector ( 3 downto 0 ) := X " 5 "

Constant

trans_type

trans_type std_logic_vector ( 3 downto 0 )

Signal

TRANS_WR

TRANS_WR std_logic_vector ( 3 downto 0 ) := X " 1 "

Constant

TRANS_WR_CFG

TRANS_WR_CFG std_logic_vector ( 3 downto 0 ) := X " 7 "

Constant

TRANS_WRN

TRANS_WRN std_logic_vector ( 3 downto 0 ) := X " 3 "

Constant

words_done

words_done unsigned ( 7 downto 0 )

Signal

words_todo

words_todo unsigned ( 7 downto 0 )

Signal

write

write std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/transactor_sm.vhd