testbench Architecture Reference

Processes
mgt_stim	( )

Constants
WORDSPERFRAME	positive := 4
ttc_period	time := 25 . 0 ns
mgt_halfperiod	time := ttc_period / ( WORDSPERFRAME * 2 )
mgt_period	time := mgt_halfperiod * 2
bc_halfperiod	time := mgt_halfperiod * WORDSPERFRAME
bc_period	time := bc_halfperiod * 2

Signals
data_clk	std_logic := ' 0 '
data_in	mgt_data
ttc_clk	std_logic := ' 0 '
crc_ignore	std_logic := ' 0 '
mgt_rx_ok	std_logic := ' 1 '
L1A	std_logic
BCR	std_logic
ECR	std_logic
crc_error	std_logic
rxdata	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
rxctrl	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
crc_bits	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Instantiations
uut	ttcinfo_sink <Entity ttcinfo_sink>

Member Function Documentation

mgt_stim()

mgt_stim

(

)

Member Data Documentation

bc_halfperiod

bc_halfperiod time := mgt_halfperiod * WORDSPERFRAME

Constant

bc_period

bc_period time := bc_halfperiod * 2

Constant

BCR

BCR std_logic

Signal

crc_bits

crc_bits std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Signal

crc_error

crc_error std_logic

Signal

crc_ignore

crc_ignore std_logic := ' 0 '

Signal

data_clk

data_clk std_logic := ' 0 '

Signal

data_in

data_in mgt_data

Signal

ECR

ECR std_logic

Signal

L1A

L1A std_logic

Signal

mgt_halfperiod

mgt_halfperiod time := ttc_period / ( WORDSPERFRAME * 2 )

Constant

mgt_period

mgt_period time := mgt_halfperiod * 2

Constant

mgt_rx_ok

mgt_rx_ok std_logic := ' 1 '

Signal

rxctrl

rxctrl std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

rxdata

rxdata std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

ttc_clk

ttc_clk std_logic := ' 0 '

Signal

ttc_period

ttc_period time := 25 . 0 ns

Constant

uut

uut ttcinfo_sink

Instantiation

WORDSPERFRAME

WORDSPERFRAME positive := 4

Constant

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The documentation for this class was generated from the following file:

• FTM/Control/testbench/ttcinfo_sink_tb.vhd