My Project  v0.0.16
Types | Signals | Processes
initial Architecture Reference

Processes

write  ( ClkA )
read  ( ClkB )
write  ( ClkA )
read  ( ClkB )
write  ( ClkA )
read  ( ClkB )

Types

ram_type ( 2 ** ( BUFWIDTH + ADDRWIDTH ) - 1 downto 0 ) std_logic_vector ( 7 downto 0 )

Signals

ram  ram_type

Member Function Documentation

◆ read() [1/3]

read (   ClkB  
)
Process

◆ read() [2/3]

read (   ClkB  
)
Process

◆ read() [3/3]

read (   ClkB  
)
Process

◆ write() [1/3]

write (   ClkA  
)
Process

◆ write() [2/3]

write (   ClkA  
)
Process

◆ write() [3/3]

write (   ClkA  
)
Process

Member Data Documentation

◆ ram

ram ram_type
Signal

◆ ram_type

ram_type ( 2 ** ( BUFWIDTH + ADDRWIDTH ) - 1 downto 0 ) std_logic_vector ( 7 downto 0 )
Type
The documentation for this class was generated from the following file:
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