ug480 Entity Reference

Inheritance diagram for ug480:

Entities
rtl	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Ports
DCLK	in STD_LOGIC
RESET	in STD_LOGIC
VAUXP	in STD_LOGIC_VECTOR ( 3 downto 0 )
VAUXN	in STD_LOGIC_VECTOR ( 3 downto 0 )
VP	in STD_LOGIC
VN	in STD_LOGIC
MEASURED_TEMP	out STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCAUX	out STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCINT	out STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCBRAM	out STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_AUX0	out STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_AUX1	out STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_AUX2	out STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_AUX3	out STD_LOGIC_VECTOR ( 15 downto 0 )
ALM	out STD_LOGIC_VECTOR ( 7 downto 0 )
CHANNEL	out STD_LOGIC_VECTOR ( 4 downto 0 )
OT	out STD_LOGIC
EOC	out STD_LOGIC
EOS	out STD_LOGIC

Member Data Documentation

ALM

ALM out STD_LOGIC_VECTOR ( 7 downto 0 )

Port

CHANNEL

CHANNEL out STD_LOGIC_VECTOR ( 4 downto 0 )

Port

DCLK

DCLK in STD_LOGIC

Port

EOC

EOC out STD_LOGIC

Port

EOS

EOS out STD_LOGIC

Port

ieee

ieee

Library

MEASURED_AUX0

MEASURED_AUX0 out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

MEASURED_AUX1

MEASURED_AUX1 out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

MEASURED_AUX2

MEASURED_AUX2 out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

MEASURED_AUX3

MEASURED_AUX3 out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

MEASURED_TEMP

MEASURED_TEMP out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

MEASURED_VCCAUX

MEASURED_VCCAUX out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

MEASURED_VCCBRAM

MEASURED_VCCBRAM out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

MEASURED_VCCINT

MEASURED_VCCINT out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

numeric_std

numeric_std

Package

OT

OT out STD_LOGIC

Port

RESET

RESET in STD_LOGIC

Port

std_logic_1164

std_logic_1164

Package

UNISIM

UNISIM

Library

VAUXN

VAUXN in STD_LOGIC_VECTOR ( 3 downto 0 )

Port

VAUXP

VAUXP in STD_LOGIC_VECTOR ( 3 downto 0 )

Port

VCOMPONENTS

VCOMPONENTS

Package

VN

VN in STD_LOGIC

Port

VP

VP in STD_LOGIC

Port

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The documentation for this class was generated from the following file:

• common/xadc/hdl/ug480.vhd