rtl Architecture Reference

Processes
NEXT_STATE_DECODE	( dclk_bufg , RESET )

Types
state_type	( init_read , read_waitdrdy , write_waitdrdy , read_reg00 , reg00_waitdrdy , read_reg01 , reg01_waitdrdy , read_reg02 , reg02_waitdrdy , read_reg06 , reg06_waitdrdy , read_reg10 , reg10_waitdrdy , read_reg11 , reg11_waitdrdy , read_reg12 , reg12_waitdrdy , read_reg13 , reg13_waitdrdy )

Signals
FLOAT_VBRAM_ALARM	STD_LOGIC
FLOAT_MUXADDR	STD_LOGIC_VECTOR ( 4 downto 0 )
den_reg	STD_LOGIC_VECTOR ( 1 downto 0 )
dwe_reg	STD_LOGIC_VECTOR ( 1 downto 0 )
vauxp_active	STD_LOGIC_VECTOR ( 15 downto 0 )
vauxn_active	STD_LOGIC_VECTOR ( 15 downto 0 )
daddr	STD_LOGIC_VECTOR ( 6 downto 0 )
den	STD_LOGIC
di_drp	STD_LOGIC_VECTOR ( 15 downto 0 )
dwe	STD_LOGIC
do_drp	STD_LOGIC_VECTOR ( 15 downto 0 )
drdy	STD_LOGIC
eoc_drp	STD_LOGIC
eos_drp	STD_LOGIC
busy	STD_LOGIC
dclk_bufg	STD_LOGIC
state	state_type
next_state	state_type

Instantiations
u_bufg	bufg
u0	xadc

Member Function Documentation

NEXT_STATE_DECODE()

NEXT_STATE_DECODE	(		dclk_bufg,
			RESET
	)

Member Data Documentation

busy

busy STD_LOGIC

Signal

daddr

daddr STD_LOGIC_VECTOR ( 6 downto 0 )

Signal

dclk_bufg

dclk_bufg STD_LOGIC

Signal

den

den STD_LOGIC

Signal

den_reg

den_reg STD_LOGIC_VECTOR ( 1 downto 0 )

Signal

di_drp

di_drp STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

do_drp

do_drp STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

drdy

drdy STD_LOGIC

Signal

dwe

dwe STD_LOGIC

Signal

dwe_reg

dwe_reg STD_LOGIC_VECTOR ( 1 downto 0 )

Signal

eoc_drp

eoc_drp STD_LOGIC

Signal

eos_drp

eos_drp STD_LOGIC

Signal

FLOAT_MUXADDR

FLOAT_MUXADDR STD_LOGIC_VECTOR ( 4 downto 0 )

Signal

FLOAT_VBRAM_ALARM

FLOAT_VBRAM_ALARM STD_LOGIC

Signal

next_state

next_state state_type

Signal

state

state state_type

Signal

state_type

state_type ( init_read , read_waitdrdy , write_waitdrdy , read_reg00 , reg00_waitdrdy , read_reg01 , reg01_waitdrdy , read_reg02 , reg02_waitdrdy , read_reg06 , reg06_waitdrdy , read_reg10 , reg10_waitdrdy , read_reg11 , reg11_waitdrdy , read_reg12 , reg12_waitdrdy , read_reg13 , reg13_waitdrdy )

Type

u0

u0 xadc

Instantiation

u_bufg

u_bufg bufg

Instantiation

vauxn_active

vauxn_active STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

vauxp_active

vauxp_active STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• common/xadc/hdl/ug480.vhd