tb Architecture Reference

Components
ug480	<Entity ug480>

Signals
DCLK	STD_LOGIC := ' 0 '
RESET	STD_LOGIC := ' 0 '
MEASURED_TEMP	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCAUX	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCINT	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCBRAM	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_AUX0	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_AUX1	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_AUX2	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_AUX3	STD_LOGIC_VECTOR ( 15 downto 0 )
ALM	STD_LOGIC_VECTOR ( 7 downto 0 )
CHANNEL	STD_LOGIC_VECTOR ( 4 downto 0 )
OT	STD_LOGIC
EOC	STD_LOGIC
EOS	STD_LOGIC
VP	STD_LOGIC
VN	STD_LOGIC

Instantiations
ug480_inst	ug480 <Entity ug480>

Member Data Documentation

ALM

ALM STD_LOGIC_VECTOR ( 7 downto 0 )

Signal

CHANNEL

CHANNEL STD_LOGIC_VECTOR ( 4 downto 0 )

Signal

DCLK

DCLK STD_LOGIC := ' 0 '

Signal

EOC

EOC STD_LOGIC

Signal

EOS

EOS STD_LOGIC

Signal

MEASURED_AUX0

MEASURED_AUX0 STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

MEASURED_AUX1

MEASURED_AUX1 STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

MEASURED_AUX2

MEASURED_AUX2 STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

MEASURED_AUX3

MEASURED_AUX3 STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

MEASURED_TEMP

MEASURED_TEMP STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

MEASURED_VCCAUX

MEASURED_VCCAUX STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

MEASURED_VCCBRAM

MEASURED_VCCBRAM STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

MEASURED_VCCINT

MEASURED_VCCINT STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

OT

OT STD_LOGIC

Signal

RESET

RESET STD_LOGIC := ' 0 '

Signal

ug480

ug480

Component

ug480_inst

ug480_inst ug480

Instantiation

VN

VN STD_LOGIC

Signal

VP

VP STD_LOGIC

Signal

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The documentation for this class was generated from the following file:

• common/xadc/sim/ug480_tb.vhd