v5_emac_v1_8_serdes Entity Reference

Inheritance diagram for v5_emac_v1_8_serdes:

Entities
WRAPPER	architecture

Libraries
unisim
ieee

Use Clauses
vcomponents
std_logic_1164

Ports
EMAC0CLIENTRXCLIENTCLKOUT	out std_logic
CLIENTEMAC0RXCLIENTCLKIN	in std_logic
EMAC0CLIENTRXD	out std_logic_vector ( 7 downto 0 )
EMAC0CLIENTRXDVLD	out std_logic
EMAC0CLIENTRXDVLDMSW	out std_logic
EMAC0CLIENTRXGOODFRAME	out std_logic
EMAC0CLIENTRXBADFRAME	out std_logic
EMAC0CLIENTRXFRAMEDROP	out std_logic
EMAC0CLIENTRXSTATS	out std_logic_vector ( 6 downto 0 )
EMAC0CLIENTRXSTATSVLD	out std_logic
EMAC0CLIENTRXSTATSBYTEVLD	out std_logic
EMAC0CLIENTTXCLIENTCLKOUT	out std_logic
CLIENTEMAC0TXCLIENTCLKIN	in std_logic
CLIENTEMAC0TXD	in std_logic_vector ( 7 downto 0 )
CLIENTEMAC0TXDVLD	in std_logic
CLIENTEMAC0TXDVLDMSW	in std_logic
EMAC0CLIENTTXACK	out std_logic
CLIENTEMAC0TXFIRSTBYTE	in std_logic
CLIENTEMAC0TXUNDERRUN	in std_logic
EMAC0CLIENTTXCOLLISION	out std_logic
EMAC0CLIENTTXRETRANSMIT	out std_logic
CLIENTEMAC0TXIFGDELAY	in std_logic_vector ( 7 downto 0 )
EMAC0CLIENTTXSTATS	out std_logic
EMAC0CLIENTTXSTATSVLD	out std_logic
EMAC0CLIENTTXSTATSBYTEVLD	out std_logic
CLIENTEMAC0PAUSEREQ	in std_logic
CLIENTEMAC0PAUSEVAL	in std_logic_vector ( 15 downto 0 )
GTX_CLK_0	in std_logic
PHYEMAC0TXGMIIMIICLKIN	in std_logic
EMAC0PHYTXGMIIMIICLKOUT	out std_logic
RXDATA_0	in std_logic_vector ( 7 downto 0 )
TXDATA_0	out std_logic_vector ( 7 downto 0 )
DCM_LOCKED_0	in std_logic
AN_INTERRUPT_0	out std_logic
SIGNAL_DETECT_0	in std_logic
PHYAD_0	in std_logic_vector ( 4 downto 0 )
ENCOMMAALIGN_0	out std_logic
LOOPBACKMSB_0	out std_logic
MGTRXRESET_0	out std_logic
MGTTXRESET_0	out std_logic
POWERDOWN_0	out std_logic
SYNCACQSTATUS_0	out std_logic
RXCLKCORCNT_0	in std_logic_vector ( 2 downto 0 )
RXBUFSTATUS_0	in std_logic_vector ( 1 downto 0 )
RXCHARISCOMMA_0	in std_logic
RXCHARISK_0	in std_logic
RXDISPERR_0	in std_logic
RXNOTINTABLE_0	in std_logic
RXREALIGN_0	in std_logic
RXRUNDISP_0	in std_logic
TXBUFERR_0	in std_logic
TXCHARDISPMODE_0	out std_logic
TXCHARDISPVAL_0	out std_logic
TXCHARISK_0	out std_logic
TXRUNDISP_0	in std_logic
RESET	in std_logic

Member Data Documentation

AN_INTERRUPT_0

AN_INTERRUPT_0 out std_logic

Port

CLIENTEMAC0PAUSEREQ

CLIENTEMAC0PAUSEREQ in std_logic

Port

CLIENTEMAC0PAUSEVAL

CLIENTEMAC0PAUSEVAL in std_logic_vector ( 15 downto 0 )

Port

CLIENTEMAC0RXCLIENTCLKIN

CLIENTEMAC0RXCLIENTCLKIN in std_logic

Port

CLIENTEMAC0TXCLIENTCLKIN

CLIENTEMAC0TXCLIENTCLKIN in std_logic

Port

CLIENTEMAC0TXD

CLIENTEMAC0TXD in std_logic_vector ( 7 downto 0 )

Port

CLIENTEMAC0TXDVLD

CLIENTEMAC0TXDVLD in std_logic

Port

CLIENTEMAC0TXDVLDMSW

CLIENTEMAC0TXDVLDMSW in std_logic

Port

CLIENTEMAC0TXFIRSTBYTE

CLIENTEMAC0TXFIRSTBYTE in std_logic

Port

CLIENTEMAC0TXIFGDELAY

CLIENTEMAC0TXIFGDELAY in std_logic_vector ( 7 downto 0 )

Port

CLIENTEMAC0TXUNDERRUN

CLIENTEMAC0TXUNDERRUN in std_logic

Port

DCM_LOCKED_0

DCM_LOCKED_0 in std_logic

Port

EMAC0CLIENTRXBADFRAME

EMAC0CLIENTRXBADFRAME out std_logic

Port

EMAC0CLIENTRXCLIENTCLKOUT

EMAC0CLIENTRXCLIENTCLKOUT out std_logic

Port

EMAC0CLIENTRXD

EMAC0CLIENTRXD out std_logic_vector ( 7 downto 0 )

Port

EMAC0CLIENTRXDVLD

EMAC0CLIENTRXDVLD out std_logic

Port

EMAC0CLIENTRXDVLDMSW

EMAC0CLIENTRXDVLDMSW out std_logic

Port

EMAC0CLIENTRXFRAMEDROP

EMAC0CLIENTRXFRAMEDROP out std_logic

Port

EMAC0CLIENTRXGOODFRAME

EMAC0CLIENTRXGOODFRAME out std_logic

Port

EMAC0CLIENTRXSTATS

EMAC0CLIENTRXSTATS out std_logic_vector ( 6 downto 0 )

Port

EMAC0CLIENTRXSTATSBYTEVLD

EMAC0CLIENTRXSTATSBYTEVLD out std_logic

Port

EMAC0CLIENTRXSTATSVLD

EMAC0CLIENTRXSTATSVLD out std_logic

Port

EMAC0CLIENTTXACK

EMAC0CLIENTTXACK out std_logic

Port

EMAC0CLIENTTXCLIENTCLKOUT

EMAC0CLIENTTXCLIENTCLKOUT out std_logic

Port

EMAC0CLIENTTXCOLLISION

EMAC0CLIENTTXCOLLISION out std_logic

Port

EMAC0CLIENTTXRETRANSMIT

EMAC0CLIENTTXRETRANSMIT out std_logic

Port

EMAC0CLIENTTXSTATS

EMAC0CLIENTTXSTATS out std_logic

Port

EMAC0CLIENTTXSTATSBYTEVLD

EMAC0CLIENTTXSTATSBYTEVLD out std_logic

Port

EMAC0CLIENTTXSTATSVLD

EMAC0CLIENTTXSTATSVLD out std_logic

Port

EMAC0PHYTXGMIIMIICLKOUT

EMAC0PHYTXGMIIMIICLKOUT out std_logic

Port

ENCOMMAALIGN_0

ENCOMMAALIGN_0 out std_logic

Port

GTX_CLK_0

GTX_CLK_0 in std_logic

Port

ieee

ieee

Library

LOOPBACKMSB_0

LOOPBACKMSB_0 out std_logic

Port

MGTRXRESET_0

MGTRXRESET_0 out std_logic

Port

MGTTXRESET_0

MGTTXRESET_0 out std_logic

Port

PHYAD_0

PHYAD_0 in std_logic_vector ( 4 downto 0 )

Port

PHYEMAC0TXGMIIMIICLKIN

PHYEMAC0TXGMIIMIICLKIN in std_logic

Port

POWERDOWN_0

POWERDOWN_0 out std_logic

Port

RESET

RESET in std_logic

Port

RXBUFSTATUS_0

RXBUFSTATUS_0 in std_logic_vector ( 1 downto 0 )

Port

RXCHARISCOMMA_0

RXCHARISCOMMA_0 in std_logic

Port

RXCHARISK_0

RXCHARISK_0 in std_logic

Port

RXCLKCORCNT_0

RXCLKCORCNT_0 in std_logic_vector ( 2 downto 0 )

Port

RXDATA_0

RXDATA_0 in std_logic_vector ( 7 downto 0 )

Port

RXDISPERR_0

RXDISPERR_0 in std_logic

Port

RXNOTINTABLE_0

RXNOTINTABLE_0 in std_logic

Port

RXREALIGN_0

RXREALIGN_0 in std_logic

Port

RXRUNDISP_0

RXRUNDISP_0 in std_logic

Port

SIGNAL_DETECT_0

SIGNAL_DETECT_0 in std_logic

Port

std_logic_1164

std_logic_1164

Package

SYNCACQSTATUS_0

SYNCACQSTATUS_0 out std_logic

Port

TXBUFERR_0

TXBUFERR_0 in std_logic

Port

TXCHARDISPMODE_0

TXCHARDISPMODE_0 out std_logic

Port

TXCHARDISPVAL_0

TXCHARDISPVAL_0 out std_logic

Port

TXCHARISK_0

TXCHARISK_0 out std_logic

Port

TXDATA_0

TXDATA_0 out std_logic_vector ( 7 downto 0 )

Port

TXRUNDISP_0

TXRUNDISP_0 in std_logic

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes.vhd