v5_emac_v1_8_serdes_block Entity Reference

Inheritance diagram for v5_emac_v1_8_serdes_block:

Collaboration diagram for v5_emac_v1_8_serdes_block:

Entities
TOP_LEVEL	architecture

Libraries
unisim
ieee

Use Clauses
vcomponents
std_logic_1164

Ports
CLK125_OUT	out std_logic
CLK125	in std_logic
CLK62_5	in std_logic
EMAC0CLIENTRXD	out std_logic_vector ( 7 downto 0 )
EMAC0CLIENTRXDVLD	out std_logic
EMAC0CLIENTRXGOODFRAME	out std_logic
EMAC0CLIENTRXBADFRAME	out std_logic
EMAC0CLIENTRXFRAMEDROP	out std_logic
EMAC0CLIENTRXSTATS	out std_logic_vector ( 6 downto 0 )
EMAC0CLIENTRXSTATSVLD	out std_logic
EMAC0CLIENTRXSTATSBYTEVLD	out std_logic
CLIENTEMAC0TXD	in std_logic_vector ( 7 downto 0 )
CLIENTEMAC0TXDVLD	in std_logic
EMAC0CLIENTTXACK	out std_logic
CLIENTEMAC0TXFIRSTBYTE	in std_logic
CLIENTEMAC0TXUNDERRUN	in std_logic
EMAC0CLIENTTXCOLLISION	out std_logic
EMAC0CLIENTTXRETRANSMIT	out std_logic
CLIENTEMAC0TXIFGDELAY	in std_logic_vector ( 7 downto 0 )
EMAC0CLIENTTXSTATS	out std_logic
EMAC0CLIENTTXSTATSVLD	out std_logic
EMAC0CLIENTTXSTATSBYTEVLD	out std_logic
CLIENTEMAC0PAUSEREQ	in std_logic
CLIENTEMAC0PAUSEVAL	in std_logic_vector ( 15 downto 0 )
EMAC0CLIENTSYNCACQSTATUS	out std_logic
EMAC0ANINTERRUPT	out std_logic
TXP_0	out std_logic
TXN_0	out std_logic
RXP_0	in std_logic
RXN_0	in std_logic
PHYAD_0	in std_logic_vector ( 4 downto 0 )
RESETDONE_0	out std_logic
TXN_1_UNUSED	out std_logic
TXP_1_UNUSED	out std_logic
RXN_1_UNUSED	in std_logic
RXP_1_UNUSED	in std_logic
CLK_DS	in std_logic
GTRESET	in std_logic
RESET	in std_logic
rxpolarity	in std_logic_vector ( 1 downto 0 )
txpolarity	in std_logic_vector ( 1 downto 0 )

Member Data Documentation

CLIENTEMAC0PAUSEREQ

CLIENTEMAC0PAUSEREQ in std_logic

Port

CLIENTEMAC0PAUSEVAL

CLIENTEMAC0PAUSEVAL in std_logic_vector ( 15 downto 0 )

Port

CLIENTEMAC0TXD

CLIENTEMAC0TXD in std_logic_vector ( 7 downto 0 )

Port

CLIENTEMAC0TXDVLD

CLIENTEMAC0TXDVLD in std_logic

Port

CLIENTEMAC0TXFIRSTBYTE

CLIENTEMAC0TXFIRSTBYTE in std_logic

Port

CLIENTEMAC0TXIFGDELAY

CLIENTEMAC0TXIFGDELAY in std_logic_vector ( 7 downto 0 )

Port

CLIENTEMAC0TXUNDERRUN

CLIENTEMAC0TXUNDERRUN in std_logic

Port

CLK125

CLK125 in std_logic

Port

CLK125_OUT

CLK125_OUT out std_logic

Port

CLK62_5

CLK62_5 in std_logic

Port

CLK_DS

CLK_DS in std_logic

Port

EMAC0ANINTERRUPT

EMAC0ANINTERRUPT out std_logic

Port

EMAC0CLIENTRXBADFRAME

EMAC0CLIENTRXBADFRAME out std_logic

Port

EMAC0CLIENTRXD

EMAC0CLIENTRXD out std_logic_vector ( 7 downto 0 )

Port

EMAC0CLIENTRXDVLD

EMAC0CLIENTRXDVLD out std_logic

Port

EMAC0CLIENTRXFRAMEDROP

EMAC0CLIENTRXFRAMEDROP out std_logic

Port

EMAC0CLIENTRXGOODFRAME

EMAC0CLIENTRXGOODFRAME out std_logic

Port

EMAC0CLIENTRXSTATS

EMAC0CLIENTRXSTATS out std_logic_vector ( 6 downto 0 )

Port

EMAC0CLIENTRXSTATSBYTEVLD

EMAC0CLIENTRXSTATSBYTEVLD out std_logic

Port

EMAC0CLIENTRXSTATSVLD

EMAC0CLIENTRXSTATSVLD out std_logic

Port

EMAC0CLIENTSYNCACQSTATUS

EMAC0CLIENTSYNCACQSTATUS out std_logic

Port

EMAC0CLIENTTXACK

EMAC0CLIENTTXACK out std_logic

Port

EMAC0CLIENTTXCOLLISION

EMAC0CLIENTTXCOLLISION out std_logic

Port

EMAC0CLIENTTXRETRANSMIT

EMAC0CLIENTTXRETRANSMIT out std_logic

Port

EMAC0CLIENTTXSTATS

EMAC0CLIENTTXSTATS out std_logic

Port

EMAC0CLIENTTXSTATSBYTEVLD

EMAC0CLIENTTXSTATSBYTEVLD out std_logic

Port

EMAC0CLIENTTXSTATSVLD

EMAC0CLIENTTXSTATSVLD out std_logic

Port

GTRESET

GTRESET in std_logic

Port

ieee

ieee

Library

PHYAD_0

PHYAD_0 in std_logic_vector ( 4 downto 0 )

Port

RESET

RESET in std_logic

Port

RESETDONE_0

RESETDONE_0 out std_logic

Port

RXN_0

RXN_0 in std_logic

Port

RXN_1_UNUSED

RXN_1_UNUSED in std_logic

Port

RXP_0

RXP_0 in std_logic

Port

RXP_1_UNUSED

RXP_1_UNUSED in std_logic

Port

rxpolarity

rxpolarity in std_logic_vector ( 1 downto 0 )

Port

std_logic_1164

std_logic_1164

Package

TXN_0

TXN_0 out std_logic

Port

TXN_1_UNUSED

TXN_1_UNUSED out std_logic

Port

TXP_0

TXP_0 out std_logic

Port

TXP_1_UNUSED

TXP_1_UNUSED out std_logic

Port

txpolarity

txpolarity in std_logic_vector ( 1 downto 0 )

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes_block.vhd