TOP_LEVEL Architecture Reference

Processes
PROCESS_249	( usrclk2 , reset_ibuf_i )
PROCESS_810	( usrclk2 , reset_ibuf_i )

Components
v5_emac_v1_8_serdes	<Entity v5_emac_v1_8_serdes>
GTX_dual_1000X	<Entity GTX_dual_1000X>

Signals
gnd_i	std_logic
vcc_i	std_logic
reset_ibuf_i	std_logic
reset_i	std_logic
reset_r	std_logic_vector ( 3 downto 0 )
rx_client_clk_out_0_i	std_logic
rx_client_clk_in_0_i	std_logic
tx_client_clk_out_0_i	std_logic
tx_client_clk_in_0_i	std_logic
emac_locked_0_i	std_logic
mgt_rx_data_0_i	std_logic_vector ( 7 downto 0 )
mgt_tx_data_0_i	std_logic_vector ( 7 downto 0 )
signal_detect_0_i	std_logic
elecidle_0_i	std_logic
encommaalign_0_i	std_logic
loopback_0_i	std_logic
mgt_rx_reset_0_i	std_logic
mgt_tx_reset_0_i	std_logic
powerdown_0_i	std_logic
rxclkcorcnt_0_i	std_logic_vector ( 2 downto 0 )
rxbuferr_0_i	std_logic
rxchariscomma_0_i	std_logic
rxcharisk_0_i	std_logic
rxdisperr_0_i	std_logic
rxlossofsync_0_i	std_logic_vector ( 1 downto 0 )
rxnotintable_0_i	std_logic
rxrundisp_0_i	std_logic
txbuferr_0_i	std_logic
txchardispmode_0_i	std_logic
txchardispval_0_i	std_logic
txcharisk_0_i	std_logic
gtx_clk_ibufg_0_i	std_logic
resetdone_0_i	std_logic
rxbufstatus_0_i	std_logic_vector ( 1 downto 0 )
txchardispmode_0_r	std_logic
txchardispval_0_r	std_logic
txcharisk_0_r	std_logic
mgt_tx_data_0_r	std_logic_vector ( 7 downto 0 )
usrclk2	std_logic
usrclk	std_logic
refclkout	std_logic
dcm_locked_gtp	std_logic
plllock_0_i	std_logic

Attributes
ASYNC_REG	string
ASYNC_REG	reset_r : signal is " TRUE "

Instantiations
gtx_dual_1000x_inst	GTX_dual_1000X <Entity GTX_dual_1000X>
v5_emac_wrapper_inst	v5_emac_v1_8_serdes <Entity v5_emac_v1_8_serdes>
gtx_dual_1000x_inst	GTX_dual_1000X <Entity GTX_dual_1000X>
v5_emac_wrapper_inst	v5_emac_v1_8_serdes <Entity v5_emac_v1_8_serdes>

Member Function Documentation

PROCESS_249()

PROCESS_249 (   usrclk2 ,   reset_ibuf_i   )

Process

PROCESS_810()

PROCESS_810 (   usrclk2 ,   reset_ibuf_i   )

Process

Member Data Documentation

ASYNC_REG [1/2]

ASYNC_REG string

Attribute

ASYNC_REG [2/2]

ASYNC_REG reset_r : signal is " TRUE "

Attribute

dcm_locked_gtp

dcm_locked_gtp std_logic

Signal

elecidle_0_i

elecidle_0_i std_logic

Signal

emac_locked_0_i

emac_locked_0_i std_logic

Signal

encommaalign_0_i

encommaalign_0_i std_logic

Signal

gnd_i

gnd_i std_logic

Signal

gtx_clk_ibufg_0_i

gtx_clk_ibufg_0_i std_logic

Signal

GTX_dual_1000X

GTX_dual_1000X

Component

gtx_dual_1000x_inst [1/2]

gtx_dual_1000x_inst GTX_dual_1000X

Instantiation

gtx_dual_1000x_inst [2/2]

gtx_dual_1000x_inst GTX_dual_1000X

Instantiation

loopback_0_i

loopback_0_i std_logic

Signal

mgt_rx_data_0_i

mgt_rx_data_0_i std_logic_vector ( 7 downto 0 )

Signal

mgt_rx_reset_0_i

mgt_rx_reset_0_i std_logic

Signal

mgt_tx_data_0_i

mgt_tx_data_0_i std_logic_vector ( 7 downto 0 )

Signal

mgt_tx_data_0_r

mgt_tx_data_0_r std_logic_vector ( 7 downto 0 )

Signal

mgt_tx_reset_0_i

mgt_tx_reset_0_i std_logic

Signal

plllock_0_i

plllock_0_i std_logic

Signal

powerdown_0_i

powerdown_0_i std_logic

Signal

refclkout

refclkout std_logic

Signal

reset_i

reset_i std_logic

Signal

reset_ibuf_i

reset_ibuf_i std_logic

Signal

reset_r

reset_r std_logic_vector ( 3 downto 0 )

Signal

resetdone_0_i

resetdone_0_i std_logic

Signal

rx_client_clk_in_0_i

rx_client_clk_in_0_i std_logic

Signal

rx_client_clk_out_0_i

rx_client_clk_out_0_i std_logic

Signal

rxbuferr_0_i

rxbuferr_0_i std_logic

Signal

rxbufstatus_0_i

rxbufstatus_0_i std_logic_vector ( 1 downto 0 )

Signal

rxchariscomma_0_i

rxchariscomma_0_i std_logic

Signal

rxcharisk_0_i

rxcharisk_0_i std_logic

Signal

rxclkcorcnt_0_i

rxclkcorcnt_0_i std_logic_vector ( 2 downto 0 )

Signal

rxdisperr_0_i

rxdisperr_0_i std_logic

Signal

rxlossofsync_0_i

rxlossofsync_0_i std_logic_vector ( 1 downto 0 )

Signal

rxnotintable_0_i

rxnotintable_0_i std_logic

Signal

rxrundisp_0_i

rxrundisp_0_i std_logic

Signal

signal_detect_0_i

signal_detect_0_i std_logic

Signal

tx_client_clk_in_0_i

tx_client_clk_in_0_i std_logic

Signal

tx_client_clk_out_0_i

tx_client_clk_out_0_i std_logic

Signal

txbuferr_0_i

txbuferr_0_i std_logic

Signal

txchardispmode_0_i

txchardispmode_0_i std_logic

Signal

txchardispmode_0_r

txchardispmode_0_r std_logic

Signal

txchardispval_0_i

txchardispval_0_i std_logic

Signal

txchardispval_0_r

txchardispval_0_r std_logic

Signal

txcharisk_0_i

txcharisk_0_i std_logic

Signal

txcharisk_0_r

txcharisk_0_r std_logic

Signal

usrclk

usrclk std_logic

Signal

usrclk2

usrclk2 std_logic

Signal

v5_emac_v1_8_serdes

v5_emac_v1_8_serdes

Component

v5_emac_wrapper_inst [1/2]

v5_emac_wrapper_inst v5_emac_v1_8_serdes

Instantiation

v5_emac_wrapper_inst [2/2]

v5_emac_wrapper_inst v5_emac_v1_8_serdes

Instantiation

vcc_i

vcc_i std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes_block.vhd