Processor_trace_module Entity Reference

Inheritance diagram for Processor_trace_module:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_UNSIGNED
NUMERIC_STD
ipbus
ipbus_decode_L1CaloHubRodTrace

Generics
ADDR_WIDTH	positive := 8
DATA_WIDTH	positive := 32

Ports
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
pp_clock	in	STD_LOGIC
reset	in	STD_LOGIC
trace_input	in	STD_LOGIC_VECTOR ( 23 downto 0 )
state	in	STD_LOGIC_VECTOR ( 7 downto 0 )
wd_event	in	STD_LOGIC
timeout_error	in	STD_LOGIC

Detailed Description

Definition at line 29 of file Processor_trace_module.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/Processor_trace_module.vhd