Processor_trace_module.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 24.03.2022 10:45:16
-- Design Name: 
-- Module Name: Processor_trace_module - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.ipbus.all;
use work.ipbus_decode_L1CaloHubRodTrace.all;
 
entity Processor_trace_module is
   generic(
        ADDR_WIDTH: positive := 8;
        DATA_WIDTH: positive := 32
    );
   Port ( 
        ipb_clk            : in std_logic;
        ipb_rst            : in std_logic;
        ipb_in             : in ipb_wbus;
        ipb_out            : out ipb_rbus;  
  
         pp_clock         : in STD_LOGIC;
         reset            : in STD_LOGIC;
         trace_input      : in STD_LOGIC_VECTOR (23 downto 0);  --connect to signals to be traced in addition to state
         state            : in STD_LOGIC_VECTOR (7 downto 0);  --processor "state" plus any other signals to trace 
--           trig_state       : in STD_LOGIC_VECTOR (7 downto 0);  --the state to trigger on
         wd_event         : in STD_LOGIC;                      --watchdog overflow signal
         timeout_error    : in STD_LOGIC                      --one pp_clock cycle timeout error pulse 
                  
);
 
 
 
end Processor_trace_module;
 
architecture RTL of Processor_trace_module is
 
component ipbus_dpram is
    generic(
        ADDR_WIDTH: positive := 8;
        DATA_WIDTH: positive := 32
    );
    port(
    
--      ipb_addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
--      ipb_rdata: out std_logic_vector(31 downto 0);
--      ipb_strobe: in std_logic;
--      ipb_write: in std_logic;
--      ipb_wdata: in std_logic_vector(DATA_WIDTH - 1 downto 0);
--      ipb_ack  : out std_logic;
--      ipb_err : out std_logic;
        
        
        clk: in std_logic;
        rst: in std_logic;
        ipb_in: in ipb_wbus;
        ipb_out: out ipb_rbus;
        rclk: in std_logic;
        we: in std_logic := '0';
        d: in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
        q: out std_logic_vector(DATA_WIDTH - 1 downto 0);
        addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0)
    );
    
 
    
end component;
 
component proc_trace is
    generic ( addr_width    : integer    := 8;
              data_width    : integer    := 32);
    Port ( clock            : in STD_LOGIC;
           reset            : in STD_LOGIC;
           trace_input      : in STD_LOGIC_VECTOR (23 downto 0);  --connect to signals to be traced in addition to state
           state            : in STD_LOGIC_VECTOR (7 downto 0);  --processor "state" plus any other signals to trace 
           trig_state       : in STD_LOGIC_VECTOR (7 downto 0);  --the state to trigger on
           wd_event         : in STD_LOGIC;                      --watchdog overflow signal
           timeout_error    : in STD_LOGIC;                      --one pp_clock cycle timeout error pulse 
           
           arm_wd           : in STD_LOGIC;       --from ipbus pulse  register
           arm_immediate    : in STD_LOGIC;       --from ipbus pulse register 
           arm_state        : in STD_LOGIC;       --from ipbus pulse register  
           arm_timeout      : in STD_LOGIC;       --from ipbus pulse  register
           
           armed            : out STD_LOGIC;      --status output to ipbus read register
           triggered        : out STD_LOGIC;      --status output to ipbus read register 
           
           read             : in STD_LOGIC;        --ipbus register read signal for the trace data out register(strobe and not we)
           reset_pointer    : in STD_LOGIC;        --reset the read pointer to start at beginning of trace again
--           trace_data_out   : out  Std_logic_vector (31 downto 0);  --trace data output to ipbus read register 
           addr_pointer     : out  std_logic_vector(addr_width-1 downto 0)
          
          ---------memory interface ---
--        rclk: in std_logic
--      we: out std_logic := '0';
--      d: out std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
--      q: in std_logic_vector(DATA_WIDTH - 1 downto 0);
--      addr: out std_logic_vector(ADDR_WIDTH - 1 downto 0)          
          
          
           );
end component;
 
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal    trig_state       :  STD_LOGIC_VECTOR (7 downto 0);  --the state to trigger on
signal   trace_control_reg_rst : std_logic;
signal   trace_control_reg_stb : std_logic; 
signal   trace_control         : std_logic_vector (31 downto 0);
 
 
signal   arm_wd           :  STD_LOGIC;       --from ipbus pulse  register
signal   arm_immediate    :  STD_LOGIC;       --from ipbus pulse register 
signal   arm_state        :  STD_LOGIC;       --
signal   arm_timeout      :  STD_LOGIC;       --from ipbus pulse  register
signal   trigger_pattern  :  std_logic_vector(31 downto 0);
signal   addr_pointer     :  std_logic_vector(addr_width-1 downto 0);
signal   trace_data_in    :  std_logic_vector(data_width-1 downto 0);
signal   trace_data_out   :  std_logic_vector(data_width-1 downto 0);
signal   armed            :  std_logic;      --status output to ipbus read register
signal   triggered        :  std_logic;
signal   ipb_read_strobe  :  std_logic;
signal   reset_pointer    :  std_logic;
signal   clear            :  std_logic;
signal   trace_reset      :  std_logic;
signal   trigger_status   :  std_logic_vector (31 downto 0);
signal   trigger_pointer  :  std_logic_vector (31 downto 0);
 
begin
 
fabric: entity work.ipbus_fabric_sel
  generic map(
    NSLV => N_SLAVES,
    SEL_WIDTH => IPBUS_SEL_WIDTH)
  port map(
   ipb_in => ipb_in,
   ipb_out => ipb_out,
 
    sel => ipbus_sel_L1CaloHubRodTrace(ipb_in.ipb_addr),
    ipb_to_slaves => ipbw,
    ipb_from_slaves => ipbr
  );
 
 
 
--------------------registers------------------------------
--pulse reg for arming the capture mech -----
Trace_Control_reg: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset => trace_control_reg_rst,
          ipbus_in => ipbw(N_SLV_TRACE_CONTROL),
          ipbus_out => ipbr(N_SLV_TRACE_CONTROL),
          stb(0) => trace_control_reg_stb,
          q(0) => trace_control
        );
trace_control_reg_rst <=  trace_control_reg_stb or ipb_rst;  
 
arm_wd          <= trace_control(0);
arm_state       <= trace_control(1);
arm_immediate   <= trace_control(2);
arm_timeout     <= trace_control(3);
clear           <= trace_control(4);
reset_pointer   <= trace_control(5) or trace_control(4);
           
 
 
 
 
trigger_status_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TRIGGER_STATUS),
          ipb_out => ipbr(N_SLV_TRIGGER_STATUS),
          slv_clk => pp_clock,
          d(0) => trigger_status,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
        
trigger_status(0) <= armed;
trigger_status(1) <= triggered;
trigger_status(31 downto 2) <= (others => '0');        
        
 
Trigger_pattern_reg: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset => ipb_rst,
          ipbus_in => ipbw(N_SLV_TRIGGER_PATTERN),
          ipbus_out => ipbr(N_SLV_TRIGGER_PATTERN),
          q(0) => trigger_pattern
        );
 
 
trig_state <= trigger_pattern(7 downto 0);
 
trigger_pointer_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TRIGGER_POINTER),
          ipb_out => ipbr(N_SLV_TRIGGER_POINTER),
          slv_clk => pp_clock,
          d(0) => trigger_pointer,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
trigger_pointer(addr_width-1 downto 0) <= addr_pointer;
trigger_pointer(31 downto addr_width) <= (others => '0');
 
trace_words_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TRACE_WORDS),
          ipb_out => ipbr(N_SLV_TRACE_WORDS),
          slv_clk => pp_clock,
          d(0) => trace_data_out,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
trace_data_in <= trace_input(23 downto 0) & "00" & state(5 downto 0);
 
trace_mem : ipbus_dpram
   generic map (
        ADDR_WIDTH =>  addr_width,
        DATA_WIDTH =>  32
    )
  PORT MAP (
    clk             => ipb_clk,
    rst             => reset,
    ipb_in          => ipbw(N_SLV_TRACE_MEMORY),
    ipb_out         => ipbr(N_SLV_TRACE_MEMORY),
    rclk            => pp_clock,
    we              => armed,
    d               => trace_data_in,
    q               => trace_data_out, 
    addr            => addr_pointer(addr_width-1 downto 0)
      
  );
 
 
--ipb_read_strobe <= ipbw(N_SLV_TRACE_MEMORY).ipb_strobe;
ipb_read_strobe <= ipbw(N_SLV_TRACE_WORDS).ipb_strobe;
trace_reset <= ipb_rst or clear or reset; 
 
controller : proc_trace 
 
    generic map ( addr_width    => addr_width,
                  data_width    => 32)
    Port map ( 
           clock            => pp_clock,
           reset            => trace_reset,
           trace_input      => trace_input,  --connect to signals to be traced in addition to state
           state            => state,        --processor "state" plus any other signals to trace 
           trig_state       => trig_state,  --the state to trigger on
           wd_event         => wd_event,              --watchdog overflow signal 
           timeout_error    => timeout_error,        --one pp_clock cycle timeout error pulse
           
           arm_wd           => arm_wd,       --from ipbus pulse  register
           arm_immediate    => arm_immediate,       --from ipbus pulse register 
           arm_state        => arm_state,       --from ipbus pulse register 
           arm_timeout      => arm_timeout,       --from ipbus pulse register  
           
           armed            => armed,      --status output to ipbus read register
           triggered        => triggered,      --status output to ipbus read register 
           
           read             => ipb_read_strobe,        --ipbus register read signal for the trace data out register(strobe and not we)
           reset_pointer    => reset_pointer,        --reset the read pointer to start at beginning of trace again
           addr_pointer  => addr_pointer
        );
 
 
 
end RTL;