proc_trace Entity Reference

Inheritance diagram for proc_trace:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_UNSIGNED

Generics
addr_width	integer := 8

Ports
clock	in	STD_LOGIC
reset	in	STD_LOGIC
trace_input	in	STD_LOGIC_VECTOR ( 23 downto 0 )
state	in	STD_LOGIC_VECTOR ( 7 downto 0 )
trig_state	in	STD_LOGIC_VECTOR ( 7 downto 0 )
wd_event	in	STD_LOGIC
timeout_error	in	STD_LOGIC
arm_wd	in	STD_LOGIC
arm_immediate	in	STD_LOGIC
arm_state	in	STD_LOGIC
arm_timeout	in	STD_LOGIC
armed	out	STD_LOGIC
triggered	out	STD_LOGIC
read	in	STD_LOGIC
reset_pointer	in	STD_LOGIC
addr_pointer	out	std_logic_vector ( addr_width- 1 downto 0 )

Detailed Description

Definition at line 55 of file proc_trace.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/proc_trace.vhd