proc_trace.vhd

----------------------------------------------------------------------------------
-- Company: University of Cambridge
-- Engineer: Ed Flaherty
-- 
-- Create Date: 01.03.2022 17:29:31
-- Design Name: 
-- Module Name: proc_trace - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
-- Trace Module for the TOB processor
-- This module can trace processor states leading up to various events 
      --Immediate trigger (capture is once, immediatly after arming) 
      --WD timer overflow (capture is continuous after arming until a WD overflow occurs. 
      --State Trigger  (capture is continuous after arming until the specified processor state occurs) 
-- The trace_data_out is the trace memory's output
 
--Connect this module to 3 ipbus registers
---   pulse register for arm signals 
---   read only register for armed and triggered status 
---   read only register for trace data out
 
 
--when the trace data out register is read, the trace memory address is decremented to provide the data from one clock earlier. 
--read the traced data register multiple times to see the trace for all of the cycles leading up to the trigger. 
 
 
 
 
      
      
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity proc_trace is
    generic ( addr_width    : integer    := 8);  --6 equates to 64 words of trace data
    Port ( 
        
    
           clock            : in STD_LOGIC;
           reset            : in STD_LOGIC;
           trace_input      : in STD_LOGIC_VECTOR (23 downto 0);  --connect to signals to be traced in addition to state
           state            : in STD_LOGIC_VECTOR (7 downto 0);  --processor "state" plus any other signals to trace 
           trig_state       : in STD_LOGIC_VECTOR (7 downto 0);  --the state to trigger on
           wd_event         : in STD_LOGIC;                      --watchdog overflow signal 
           timeout_error    : in STD_LOGIC;                      --one pp_clock cycle timeout error pulse
           
           arm_wd           : in STD_LOGIC;       --from ipbus pulse register
           arm_immediate    : in STD_LOGIC;       --from ipbus pulse register 
           arm_state        : in STD_LOGIC;       --from ipbus pulse register  
           arm_timeout      : in STD_LOGIC;       --from ipbus pulse register  
           
           armed            : out STD_LOGIC;      --status output to ipbus read register
           triggered        : out STD_LOGIC;      --status output to ipbus read register 
           
           read             : in STD_LOGIC;        --ipbus register read signal for the trace data out register(strobe and not we)
           reset_pointer    : in STD_LOGIC;        --reset the read pointer to start at beginning of trace again
  --         trace_data_out   : out  Std_logic_vector (31 downto 0);  --trace data output to ipbus read register 
           addr_pointer     : out  std_logic_vector(addr_width-1 downto 0)
          
          
           
          
           );
end proc_trace;
 
architecture RTL of proc_trace is
 
 
--COMPONENT default_reg_ila
--
--PORT (
--  clk : IN STD_LOGIC;
--  probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
--  probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
--  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)--;
--
--);
--END COMPONENT  ;
 
 
 
signal    addr_pointer_i      :  Std_logic_vector (addr_width-1 downto 0);
signal    pointer_snap      :  Std_logic_vector (15 downto 0);
signal    trace_data_in  :  Std_logic_vector (31 downto 0);
 
signal    write             :  std_logic;
signal    read_sync         :  std_logic;
signal    read_dly          :  std_logic;
signal    arm               :  std_logic;
signal    armed_i           :  std_logic;
signal    trigger           :  std_logic; 
signal    read_pulse        : std_logic;   --synced to clock from ipbus 
signal    arm_wd_sync       : std_logic;
signal    arm_wd_dly        : std_logic;
signal    armed_wd          : std_logic;
signal    arm_wd_pulse      : std_logic;
 
signal    arm_timeout_sync  : std_logic;
signal    arm_timeout_dly   : std_logic;
signal    armed_timeout       : std_logic;
signal    arm_timeout_pulse : std_logic;
 
 
signal    arm_state_sync      : std_logic;  --sync from ipbus clock to processor clock 
signal    arm_state_dly       : std_logic; 
signal    arm_state_pulse     : std_logic; 
signal    armed_state         : std_logic;  
signal    triggered_state     : std_logic;
signal    trigger_state       : std_logic; 
--signal    trig_state          : std_logic;
 
signal    arm_imm_sync      : std_logic;  --sync from ipbus clock to processor clock 
signal    arm_imm_dly       : std_logic; 
signal    arm_imm_pulse     : std_logic; 
signal    armed_imm         : std_logic;  
signal    triggered_imm     : std_logic;
signal    address_max       : std_logic_vector(addr_width-1 downto 0);
 
 
signal   armed_wd_dly       : std_logic := '0'; 
signal   armed_timeout_dly  : std_logic := '0';   
signal   armed_state_dly    : std_logic := '0'; 
signal   armed_imm_dly      : std_logic := '0';
signal    triggered_dly     : std_logic := '0';
signal    save_pointer      : std_logic := '0';
signal    saved_pointer     :  Std_logic_vector (addr_width-1 downto 0);
 
 
 
 
begin
 
 
address_max <= (others => '1'); 
 
arm <= arm_wd;
trigger <= wd_event; 
write <= (armed_wd and not wd_event) or (armed_state and not trigger_state) or (armed_imm and not triggered_imm) or (armed_timeout and not timeout_error);
triggered <= not armed_i;
 
armed_i <= armed_wd or armed_imm or armed_state or armed_timeout;  
armed <= armed_i;
 
 
process (clock) begin
  if rising_edge(clock) then 
      read_sync  <= read;     --sync from ipbus clock to processor clock 
      read_dly <= read_sync;  --cread a delayed read_sync
  end if;
end process;
 
read_pulse <= not read_sync and read_dly;  --falling edge of read_sync
      
      
 
 
process (clock) begin
  if rising_edge(clock) then 
      if (reset_pointer = '1') then 
        addr_pointer_i <= saved_pointer;  
      elsif (reset = '1') or (arm_wd_pulse = '1') or (arm_imm_pulse = '1') or (arm_state_pulse = '1')or (arm_timeout_pulse = '1')  then 
        addr_pointer_i <= (others => '0');
      elsif write = '1' then 
        addr_pointer_i <= addr_pointer_i + 1;
      elsif read_pulse = '1' then 
        addr_pointer_i <= addr_pointer_i - 1; 
      else
        addr_pointer_i <= addr_pointer_i;
      end if;       
   end if; 
end process;
 
addr_pointer <= addr_pointer_i;
 
 
        
 
--trace_data_in <= addr_pointer & x"00" & "00" & state(5 downto 0);
trace_data_in <= trace_input(23 downto 0) & "00" & state(5 downto 0);
       
--trace_mem : trace_memory
--  PORT MAP (
--    a => addr_pointer(addr_width-1 downto 0),
--    d => trace_data_in,
--    clk => clock,
--    we => armed_i,
--    spo => trace_data_out
--  );
 
 
-- trace_mem : ipbus_dpram
--   PORT MAP (
--     addr => addr_pointer_i(addr_width-1 downto 0),
--     d => trace_data_in,
--     we => armed_i,   
--     ipb_addr        => ipb_addr, 
--     ipb_rdata       => ipb_rdata,
--  ipb_strobe     => ipb_strobe,
--  ipb_write      => ipb_write,
--  ipb_wdata      => ipb_wdata,
--  ipb_ack        => ipb_ack,
--  ipb_err        => ipb_err,
        
        
--  clk           => ipb_clk,
  --   rst          => reset,
--      ipb_in: in ipb_wbus;
--      ipb_out: out ipb_rbus;
--  rclk           => clock,
--  q              =>   trace_data_out 
 
    
    
--   );
 
 
---Watchdog trigger controls -----
 
process (clock) begin
  if rising_edge(clock) then 
      arm_wd_sync  <= arm_wd;     --sync from ipbus clock to processor clock 
      arm_wd_dly <= arm_wd_sync;             --cread a delayed arm_immediate_sync
  end if;
end process;
arm_wd_pulse <= not arm_wd_sync and arm_wd_dly;  --falling edge 
 
 
 
process (clock) begin
  if rising_edge(clock) then 
      if (reset = '1') or ((wd_event = '1') and (armed_wd = '1')) then
        armed_wd <= '0'; 
      elsif arm_wd_pulse = '1' then 
        armed_wd <= '1';
      else 
        armed_wd <= armed_wd; 
      end if; 
  end if;
 end process;          
        
        
---Timeout trigger controls -----        
process (clock) begin
  if rising_edge(clock) then 
      arm_timeout_sync  <= arm_timeout;     --sync from ipbus clock to processor clock 
      arm_timeout_dly <= arm_timeout_sync;             --cread a delayed arm_immediate_sync
  end if;
end process;
arm_timeout_pulse <= not arm_timeout_sync and arm_timeout_dly;  --falling edge         
        
process (clock) begin
  if rising_edge(clock) then 
      if (reset = '1') or ((timeout_error = '1') and (armed_timeout = '1')) then
        armed_timeout <= '0'; 
      elsif arm_timeout_pulse = '1' then 
        armed_timeout <= '1';
      else 
        armed_timeout <= armed_timeout; 
      end if; 
  end if;
 end process;                 
        
        
 
----state trigger controls 
process (clock) begin
  if rising_edge(clock) then 
      arm_state_sync  <= arm_state;     --sync from ipbus clock to processor clock 
      arm_state_dly <= arm_state_sync;             --create a delayed arm__sync
  end if;
end process;
arm_state_pulse <= not arm_state_sync and arm_state_dly;  --falling edge of arm__sync
 
trigger_state <= '1' when (state = trig_state) else '0';
 
process (clock) begin
  if rising_edge(clock) then 
      if (reset = '1') or ((trigger_state = '1') and (armed_state = '1')) then
        armed_state <= '0'; 
      elsif arm_state_pulse = '1' then 
        armed_state <= '1';
      else 
        armed_state <= armed_state; 
      end if; 
  end if;
 end process;  
 
 
 
 
 
 
---immediate trigger controls;  If user does arm_immediate, the memory first fills once and then troggers.  
 
process (clock) begin
  if rising_edge(clock) then 
      arm_imm_sync  <= arm_immediate;     --sync from ipbus clock to processor clock 
      arm_imm_dly <= arm_imm_sync;             --cread a delayed arm_immediate_sync
  end if;
end process;
arm_imm_pulse <= not arm_imm_sync and arm_imm_dly;  --falling edge of arm_imm_sync
 
 
process (clock) begin
  if rising_edge(clock) then
    if (reset = '1') or (triggered_imm = '1')  then 
         armed_imm <= '0';
    
    elsif arm_imm_pulse = '1' then 
 --       pointer_snap <= addr_pointer - 1;
        armed_imm   <= '1';
    else
 --       pointer_snap <= pointer_snap;
        armed_imm <= armed_imm;    
      end if; 
  end if;
  
end process;             
       
       
 process (clock) begin
  if rising_edge(clock) then   
     if ((reset = '1') or (arm_imm_sync = '1')) then   
        triggered_imm <= '0';
      
 --    elsif (addr_pointer(addr_width-1 downto 0) = pointer_snap(addr_width-1 downto 0)) then 
 --     elsif addr_pointer(addr_width-1 downto 0) = "111111" then
     elsif addr_pointer_i(addr_width-1 downto 0) = address_max then
        triggered_imm <= '1';
     else        
        triggered_imm <= triggered_imm;
     end if; 
  end if;
  
end process;         
 
 
 
 
 
 
 
 process (clock) begin
  if rising_edge(clock) then  
       armed_wd_dly <= armed_wd; 
       armed_timeout_dly <= armed_timeout; 
       armed_state_dly <= armed_state;
       armed_imm_dly <= armed_imm;
         
  end if; 
end process;
       
save_pointer <= (armed_wd_dly and not armed_wd) or (armed_state_dly and not armed_state) or (armed_imm_dly and not armed_imm) or (armed_timeout_dly and not armed_timeout) ;
 
process (clock) begin
  if rising_edge(clock) then  
    if save_pointer = '1' then 
        saved_pointer <= addr_pointer_i;
    else
        saved_pointer <= saved_pointer;     
    end if; 
  end if;  
end process;   
 
--trigger_ila : default_reg_ila
--PORT MAP (
--clk => clock,
--   probe0(addr_width -1 downto 0)    => addr_pointer_i,  --32
--   probe0(31) => armed,
--   probe0(30 downto addr_width) => (others => '0'),
--   probe1(0)    => arm_immediate,      --3
--   probe1(31 downto 1) => (others => '0'),
--   probe2(0) => arm_imm_pulse, 
--   probe3(0) => armed_imm 
--);  
 
 
     
 
 
end RTL;