ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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Processes | Signals
RTL Architecture Reference

Processes

PROCESS_249  ( clock )
PROCESS_250  ( clock )
PROCESS_251  ( clock )
PROCESS_252  ( clock )
PROCESS_253  ( clock )
PROCESS_254  ( clock )
PROCESS_255  ( clock )
PROCESS_256  ( clock )
PROCESS_257  ( clock )
PROCESS_258  ( clock )
PROCESS_259  ( clock )
PROCESS_260  ( clock )
PROCESS_261  ( clock )

Signals

addr_pointer_i  Std_logic_vector ( addr_width- 1 downto 0 )
pointer_snap  Std_logic_vector ( 15 downto 0 )
trace_data_in  Std_logic_vector ( 31 downto 0 )
write  std_logic
read_sync  std_logic
read_dly  std_logic
arm  std_logic
armed_i  std_logic
trigger  std_logic
read_pulse  std_logic
arm_wd_sync  std_logic
arm_wd_dly  std_logic
armed_wd  std_logic
arm_wd_pulse  std_logic
arm_timeout_sync  std_logic
arm_timeout_dly  std_logic
armed_timeout  std_logic
arm_timeout_pulse  std_logic
arm_state_sync  std_logic
arm_state_dly  std_logic
arm_state_pulse  std_logic
armed_state  std_logic
triggered_state  std_logic
trigger_state  std_logic
arm_imm_sync  std_logic
arm_imm_dly  std_logic
arm_imm_pulse  std_logic
armed_imm  std_logic
triggered_imm  std_logic
address_max  std_logic_vector ( addr_width- 1 downto 0 )
armed_wd_dly  std_logic := ' 0 '
armed_timeout_dly  std_logic := ' 0 '
armed_state_dly  std_logic := ' 0 '
armed_imm_dly  std_logic := ' 0 '
triggered_dly  std_logic := ' 0 '
save_pointer  std_logic := ' 0 '
saved_pointer  Std_logic_vector ( addr_width- 1 downto 0 )

Detailed Description

Definition at line 87 of file proc_trace.vhd.


The documentation for this class was generated from the following file: