RTL Architecture Reference

Components
aurora_in_fifo_512
processor_in_fifo_4k

Signals
mid_fifo_tvalid	std_logic
mid_fifo_tready	std_logic
mid_fifo_tdata	std_logic_vector ( 63 downto 0 )
mid_fifo_tlast	std_logic
mid_fifo_tuser	std_logic_vector ( 3 downto 0 )
axis_data_count_i	std_logic_vector ( 31 downto 0 )
axis_data_count	std_logic_vector ( 31 downto 0 )

Instantiations
clk_cross_fifo	aurora_in_fifo_512
input_fifo	processor_in_fifo_4k

Detailed Description

Definition at line 60 of file dual_input_fifo_4k.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/dual_input_fifo_4k.vhd