dual_input_fifo_4k.vhd

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-- Company: 
-- Engineer:  
-- 
-- Create Date: 10.01.2022 16:30:58
-- Design Name: 
-- Module Name: input_buffer_4k - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity dual_input_fifo_4k is
  Port ( 
    m_aclk              : IN STD_LOGIC;
    s_aclk              : IN STD_LOGIC;
    s_aresetn           : IN STD_LOGIC;
    s_axis_tvalid       : IN STD_LOGIC;
    s_axis_tready       : OUT STD_LOGIC;
    s_axis_tdata        : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    s_axis_tlast        : IN STD_LOGIC;
    s_axis_tuser        : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axis_tvalid       : OUT STD_LOGIC;
    m_axis_tready       : IN STD_LOGIC;
    m_axis_tdata        : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    m_axis_tlast        : OUT STD_LOGIC;
    m_axis_tuser        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    axis_wr_data_count  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    axis_rd_data_count  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
    
    
  );  
    
    
    
  
end dual_input_fifo_4k;
 
architecture RTL of dual_input_fifo_4k is
 
 
 
COMPONENT aurora_in_fifo_512
  PORT (
    wr_rst_busy : OUT STD_LOGIC;
    rd_rst_busy : OUT STD_LOGIC;
    m_aclk : IN STD_LOGIC;
    s_aclk : IN STD_LOGIC;
    s_aresetn : IN STD_LOGIC;
    s_axis_tvalid : IN STD_LOGIC;
    s_axis_tready : OUT STD_LOGIC;
    s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    s_axis_tlast : IN STD_LOGIC;
    s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axis_tvalid : OUT STD_LOGIC;
    m_axis_tready : IN STD_LOGIC;
    m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    m_axis_tlast : OUT STD_LOGIC;
    m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    axis_wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
    axis_rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
  );
END COMPONENT;
 
COMPONENT processor_in_fifo_4k
  PORT (
    wr_rst_busy : OUT STD_LOGIC;
    rd_rst_busy : OUT STD_LOGIC;
    s_aclk : IN STD_LOGIC;
    s_aresetn : IN STD_LOGIC;
    s_axis_tvalid : IN STD_LOGIC;
    s_axis_tready : OUT STD_LOGIC;
    s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    s_axis_tlast : IN STD_LOGIC;
    s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axis_tvalid : OUT STD_LOGIC;
    m_axis_tready : IN STD_LOGIC;
    m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    m_axis_tlast : OUT STD_LOGIC;
    m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    axis_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
  );
END COMPONENT;
 
signal  mid_fifo_tvalid : std_logic; 
signal  mid_fifo_tready : std_logic; 
signal  mid_fifo_tdata  : std_logic_vector(63 downto 0);
signal  mid_fifo_tlast  : std_logic;
signal  mid_fifo_tuser  : std_logic_vector(3 downto 0);
signal  axis_data_count_i : std_logic_vector(31 downto 0);
signal  axis_data_count : std_logic_vector(31 downto 0);
begin
 
 
clk_cross_fifo : aurora_in_fifo_512
PORT MAP (
    wr_rst_busy => open,
    rd_rst_busy => open,
    m_aclk => m_aclk,
    s_aclk => s_aclk,
    s_aresetn => s_aresetn,
    s_axis_tvalid => s_axis_tvalid,
    s_axis_tready => s_axis_tready,
    s_axis_tdata => s_axis_tdata,
    s_axis_tlast => s_axis_tlast,
    s_axis_tuser => s_axis_tuser,
--    s_axis_tuser(0) => first_cyc,
--    s_axis_tuser(1) => pipe_m_axis_tlast,
--    s_axis_tuser(2) => s_crc_error,
--    s_axis_tuser(3) => pipe_m_comb_error,  
    m_axis_tvalid   => mid_fifo_tvalid,
    m_axis_tready   => mid_fifo_tready,
    m_axis_tdata    => mid_fifo_tdata,
    m_axis_tlast    => mid_fifo_tlast,
    m_axis_tuser    => mid_fifo_tuser,
    axis_wr_data_count => open,
    axis_rd_data_count => open
);
 
input_fifo : processor_in_fifo_4k
PORT MAP (
    wr_rst_busy => open,
    rd_rst_busy => open,
    s_aclk => m_aclk,
    s_aresetn => s_aresetn,
    s_axis_tvalid => mid_fifo_tvalid,
    s_axis_tready => mid_fifo_tready,
    s_axis_tdata => mid_fifo_tdata,
    s_axis_tlast => mid_fifo_tlast,
    s_axis_tuser    => mid_fifo_tuser,  
    m_axis_tvalid   =>  m_axis_tvalid,
    m_axis_tready   =>  m_axis_tready,
    m_axis_tdata    =>  m_axis_tdata,
    m_axis_tlast    =>  m_axis_tlast,
    m_axis_tuser    =>  m_axis_tuser,
    axis_data_count => axis_data_count_i(12 downto 0)
);
axis_data_count <=  x"0000" & "000" &  axis_data_count_i(12 downto 0);
 
axis_rd_data_count <= axis_data_count;
axis_wr_data_count <= axis_data_count;
 
end RTL;