RTL Architecture Reference

Processes
PROCESS_156	( clock )
PROCESS_157	( clock )

Components
osum_crc9d32	<Entity osum_crc9d32>

Signals
CRC_d_in	std_logic_vector ( 31 downto 0 )
cyc_1	std_logic := ' 0 '
cyc_2	std_logic := ' 0 '
cyc_3	std_logic := ' 0 '
crc_valid_i	std_logic := ' 0 '
state_sequence	std_logic_vector ( 2 downto 0 )
crc_result	std_logic_vector ( 8 downto 0 )
crc_out_reg	std_logic_vector ( 8 downto 0 ) := 9x " 00 "

Instantiations
hdr_chk_crc	osum_crc9d32 <Entity osum_crc9d32>

Detailed Description

Definition at line 61 of file event_hdr_crc9.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/event_hdr_crc9.vhd