event_hdr_crc9.vhd

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-- Company: University of Cambridge
-- Engineer: Ed Flaherty
-- 
-- Create Date: 25.09.2018 14:22:06
-- Design Name: 
-- Module Name: event_hdr_crc9 - RTL
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-- This block generates the crc9 for the outgoing event header
-- since there are 3 * 32-bit header words going out, it takes 3 cycles to generate the crc 
-- in order to avoid a dead cycle, the first word of the crc is processed while the controller is in "idle"
-- this is possible because crc start can be continuously asserted while in idle, and the output will only be 
-- a function of the input.   The input will become valid during idle because the TTC fifo is a fall through, 
-- allowing the first BCN to be stable on the output before reading the fifo. 
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-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity event_hdr_crc9 is
    Port ( 
         clock : in STD_LOGIC;
         crc_reset      : in STD_LOGIC;  --connect to hdr_sel_2 in the level above
         BCN            :  in STD_LOGIC_VECTOR (11 downto 0); 
         version        :  in STD_LOGIC_VECTOR (2 downto 0);
         tob_stream_id  :  in STD_LOGIC_VECTOR (7 downto 0);
         ECRID          :  in STD_LOGIC_VECTOR (7 downto 0);
         L1ID           :  in STD_LOGIC_VECTOR (23 downto 0);
--         header_reg_0  :  in STD_LOGIC_VECTOR (31 downto 0);
         header_reg_1  :  in STD_LOGIC_VECTOR (31 downto 0);
         header_reg_2  :  in STD_LOGIC_VECTOR (31 downto 0);
         crc_start : in STD_LOGIC;  --connect to (hdr_out_crc9_start and ttc_valid) in the level above 
         load_hdr_reg  : in STD_LOGIC;
         CRC_out       : out  STD_LOGIC_VECTOR (8 downto 0); 
         hdr_out_crc9_valid     : out  STD_LOGIC      
         );
end event_hdr_crc9;
 
architecture RTL of event_hdr_crc9 is
component osum_crc9d32 
   port(
    clock : in std_logic;
 
    crc_start : in std_logic;
    d_in      : in std_logic_vector(31 downto 0);
 
    crc_out : out std_logic_vector(8 downto 0)
    );
    
end component;
signal CRC_d_in :  std_logic_vector(31 downto 0);
--signal crc_din_reg  :  std_logic_vector(31 downto 0);
signal cyc_1      :   std_logic:='0';
signal cyc_2      :  std_logic:='0';
signal cyc_3      :  std_logic:='0';
signal crc_valid_i        :  std_logic:='0';
signal state_sequence   : std_logic_vector(2 downto 0);
signal crc_result       : std_logic_vector(8 downto 0); 
signal crc_out_reg      : std_logic_vector(8 downto 0) := 9x"00";
 
 
begin
hdr_chk_crc : osum_crc9d32
 port map( 
          clock     =>  clock,
          
--          CRC_out   =>  CRC_out,
          CRC_out   => crc_result,
--          crc_start =>  crc_start,
          crc_start =>  load_hdr_reg,
          d_in      =>  CRC_d_in
--          Reset  =>  reset
          );
 
-- wait two cycles and then capture the crc calculation result
process (clock) begin
    if rising_edge (clock) then
       if (crc_reset = '1') then 
          cyc_1 <= '0';
          cyc_2 <= '0';
          cyc_3 <= '0';
 
       else 
--          cyc_1 <= load_hdr_reg;
----          cyc_2 <= cyc_1;
--           cyc_2 <= crc_start;
--           cyc_3 <= cyc_2;
           
           
          cyc_1 <= load_hdr_reg;
          cyc_2 <= cyc_1;
          cyc_3 <= cyc_2;          
           
           
       end if; 
    end if;   
end process;
 
 
 
 
--state_sequence <= crc_start & load_hdr_reg & cyc_1;
 state_sequence <= load_hdr_reg & cyc_1 & cyc_2;
 
with state_sequence select
        CRC_d_in     <= version & "000000000" & BCN & tob_stream_id   when  "100",             
                        ECRID & L1ID                                  when   "010",
                        header_reg_2                                  when   "001",
                        x"00000000"                                   when others;
                        
 
--the crc result needs to be saved for header building 
process (clock) begin
    if rising_edge (clock) then
       if (crc_reset = '1') then 
          crc_out_reg <= 9x"00";
          crc_valid_i   <= '0';
       elsif (cyc_3 = '1') then 
          crc_out_reg <= crc_result;
          crc_valid_i   <= '1';
       else 
          crc_out_reg <= crc_out_reg;
       end if;
     end if;  
end process;
 
with cyc_3 select
     crc_out <= crc_result     when '1',
              crc_out_reg      when others;
     
 with cyc_3 select
     hdr_out_crc9_valid <= '1'     when '1',
              crc_valid_i          when others;    
     
--hdr_out_crc9_valid <= crc_valid_i;
 
end RTL;