RTL Architecture Reference

Processes
PROCESS_158	( clock )
PROCESS_159	( clock )
PROCESS_160	( clock )
PROCESS_161	( clock )
PROCESS_162	( clock )
PROCESS_163	( clock )
PROCESS_164	( clock )
PROCESS_165	( clock )

Signals
samp_0	std_logic_vector ( 17 downto 0 )
samp_1	std_logic_vector ( 17 downto 0 )
samp_2	std_logic_vector ( 17 downto 0 )
samp_3	std_logic_vector ( 17 downto 0 )
event_time_i	std_logic_vector ( 15 downto 0 ) := x " 0000 "
timer	std_logic_vector ( 16 downto 0 )
watermark_i	std_logic_vector ( 15 downto 0 ) := x " 0000 "
run	std_logic := ' 0 '
clr_timer	std_logic
stop_timer	std_logic := ' 0 '
start_timer	std_logic := ' 0 '
stop_dly	std_logic := ' 0 '
start_dly	std_logic := ' 0 '
stop_pulse	std_logic
start_pulse	std_logic
samp_sum	std_logic_vector ( 17 downto 0 ) := 18x " 00000 "

Detailed Description

Definition at line 53 of file event_timer.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/event_timer.vhd