event_timer.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 03.03.2022 11:38:31
-- Design Name: 
-- Module Name: event timer - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity event_timer is
    generic ( start_state  : std_logic_vector    := x"12";   --read_ttc         := x"02";   --start_reading 
              stop_state   : std_logic_vector    := x"11"    --wait for event
             );
    
    Port ( clock         : in STD_LOGIC;  --processor clock
           reset         : in STD_LOGIC;  --reset from a pulse register or reset 
           current_state : in STD_LOGIC_vector (7 downto 0); --current_state of the processor
           
          
           event_time    : out std_logic_vector(15 downto 0) ;   --duration of last event processing - route to ipbus register 
           watermark     : out std_logic_vector(15 downto 0);    --largest duration recorded  -  route to ipbus register 
           avg_time      : out std_logic_vector(15 downto 0)     --average duration of event processing - route to ipbus register 
                                                                --total 30 bits can be connected to a single read-only register 
           
           );
end event_timer;
 
architecture RTL of event_timer is
 
signal    samp_0        : std_logic_vector(17 downto 0);
signal    samp_1        : std_logic_vector(17 downto 0);
signal    samp_2        : std_logic_vector(17 downto 0);
signal    samp_3        : std_logic_vector(17 downto 0);
signal    event_time_i  : std_logic_vector(15 downto 0) := x"0000";
signal    timer         : std_logic_vector(16 downto 0);
signal    watermark_i     : std_logic_vector(15 downto 0) := x"0000";
signal    run           : std_logic :=  '0';
signal    clr_timer     : std_logic;
signal    stop_timer    : std_logic := '0';
signal    start_timer   : std_logic := '0';
signal    stop_dly      : std_logic := '0';
signal    start_dly     : std_logic := '0';
signal    stop_pulse    : std_logic ;
signal    start_pulse   : std_logic ;
signal    samp_sum      : std_logic_vector(17 downto 0) := 18x"00000";
--signal    avg_time_i    : std_logic_vector(9 downto 0) := 10x"000";
 
begin
 
 
--start/stop pulses (processor may stay in state for multiple cycles 
process (clock) begin 
  if rising_edge(clock) then 
      if (current_state = stop_state) then 
         stop_timer  <= '1';
      else 
         stop_timer <=  '0';
      end if; 
   end if; 
end process;    
         
 process (clock) begin 
  if rising_edge(clock) then 
      if (current_state = start_state) then 
         start_timer  <= '1';
      else 
         start_timer <=  '0';
      end if; 
   end if; 
end process;      
      
process (clock) begin 
  if rising_edge(clock) then 
         start_dly  <= start_timer;
         stop_dly   <= stop_timer; 
  end if; 
end process;               
 
start_pulse <= start_timer and not start_dly; 
stop_pulse  <= stop_timer and not stop_dly; 
 
 
 
---start/stop control -------
process (clock) begin 
  if rising_edge(clock) then 
      if (reset = '1') or (stop_pulse = '1') then 
         run <= '0';
      elsif (start_pulse = '1') then 
         run <= '1';
      else 
         run <= run;
      end if; 
   end if; 
end process; 
 
 
 
--Event duration counter/timer-----
process (clock) begin 
  if rising_edge(clock) then 
    if (reset = '1') or (stop_pulse = '1') then 
       timer <= (others => '0');
    elsif (run = '1') and (timer /= x"1FFFF") then  
       timer <= (timer + 1);  
    else 
       timer <= timer;
    end if; 
   end if;        
end process;
 
 
process (clock) begin 
  if rising_edge(clock) then 
     if (reset = '1') then 
        event_time_i <=  (others => '0'); 
        samp_0 <=  (others => '0'); 
        samp_1 <=  (others => '0');
        samp_2 <=  (others => '0'); 
        samp_3 <=  (others => '0'); 
     elsif stop_pulse = '1' then 
        event_time_i <= timer(16 downto 1); 
        samp_0(15 downto 0) <= timer(16 downto 1); 
        samp_1 <= samp_0;
        samp_2 <= samp_1; 
        samp_3 <= samp_2; 
      else
        event_time_i <= event_time_i; 
        samp_0 <= samp_0; 
        samp_1 <= samp_1;
        samp_2 <= samp_2; 
        samp_3 <= samp_3;  
      end if; 
   end if;     
 end process; 
  
 event_time <= event_time_i;
 
 
---record largest time taken
 
process (clock) begin 
  if rising_edge(clock) then 
    if (reset = '1') then 
         watermark_i <= (others => '0');
    elsif (stop_pulse = '1') and (timer(16 downto 1) > watermark_i) then 
         watermark_i <= timer(16 downto 1); 
    else    
         watermark_i <= watermark_i;
    end if; 
  end if; 
end process; 
watermark <= watermark_i;
            
 
--calculate running average of last 4 events 
 
process (clock) begin 
  if rising_edge(clock) then  
         samp_sum <= (samp_0 + samp_1 + samp_2 + samp_3); 
  end if; 
end process;          
 
--avg_time <= "00" & samp_sum(17 downto 2);
avg_time <= samp_sum(17 downto 2);
         
   
end RTL;