RTL Architecture Reference

Processes
PROCESS_185	( clock )
PROCESS_186	( clock )
PROCESS_187	( clock )

Components
osum_crc9d32	<Entity osum_crc9d32>

Signals
CRC_d_in	std_logic_vector ( 31 downto 0 )
din_reg	std_logic_vector ( 31 downto 0 )
declared_crc_reg	std_logic_vector ( 8 downto 0 )
cyc_1	std_logic
cyc_2	std_logic
crc_error	std_logic
CRC_out	std_logic_vector ( 8 downto 0 )

Instantiations
hdr_chk_crc	osum_crc9d32 <Entity osum_crc9d32>

Detailed Description

Definition at line 50 of file hdr_in_crc9.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/hdr_in_crc9.vhd