hdr_in_crc9.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 10.09.2018 18:14:37
-- Design Name: 
-- Module Name: hdr_in_crc9 - RTL
-- Project Name: L1Calo ROD 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
--this block checks the header crc on incoming TOB packets from all channels   
--if any header has a crc error, the header_mismatch flag is set.  
--the header_mismatch is cleared at the beginning of each event building 
--the the header_mismatch is incorporated into the Event packet trailer Control Error MAp    
 
 
entity hdr_in_crc9 is
    Port ( 
    clock   : in STD_LOGIC;
    crc_reset : in STD_LOGIC;  --connect to ld_hdr_reg in the level above
    s_tdata : in STD_LOGIC_VECTOR (63 downto 0);
    crc_start : in STD_LOGIC;  --connect to poll in the level above 
    header_mismatch : out std_logic
    );
end hdr_in_crc9;
 
architecture RTL of hdr_in_crc9 is
 
 
component osum_crc9d32 
   port(
    clock : in std_logic;
 
    crc_start : in std_logic;
    d_in      : in std_logic_vector(31 downto 0);
 
    crc_out : out std_logic_vector(8 downto 0)
    );
end component;
 
signal CRC_d_in :  std_logic_vector(31 downto 0);
signal din_reg  :  std_logic_vector(31 downto 0);
signal declared_crc_reg  :  std_logic_vector(8 downto 0);
signal cyc_1      :  std_logic;
signal cyc_2      :  std_logic;
signal crc_error  :  std_logic;
signal CRC_out    :  std_logic_vector(8 downto 0);
--signal header_mismatch  : std_logic;
 
begin
 
hdr_chk_crc : osum_crc9d32
 port map( 
          clock     =>  clock,
          CRC_out   =>  CRC_out,
          crc_start =>  crc_start,
          d_in      =>  CRC_d_in
--          Reset  =>  reset
          );
 
--register the upper 32-bits (second word) of the header because the header will dissapear in the next cycle
 
process (clock) begin
    if rising_edge (clock) then
       if (crc_start = '1') then 
          din_reg <= s_tdata(63 downto 32);
          declared_crc_reg <= s_tdata(28 downto 20);
       end if; 
    end if;   
end process;
 
--first mux the lower 32-bits of header (with 0 in the crc field) because it should be first into the crc 
--on the second cycle, mux in the registered upper 32-bits (second word) of the header   
 with crc_start select
        CRC_d_in     <= s_tdata(31 downto 29) & "000000000" & s_tdata(19 downto 0) when  '1',                 
                        din_reg (31 downto 0)   when others;
 
 
-- wait two cycles and then capture the crc calculation result
process (clock) begin
    if rising_edge (clock) then
       if (crc_reset = '1') then 
          cyc_1 <= '0';
          cyc_2 <= '0';
       else 
          cyc_1 <= crc_start;
          cyc_2 <= cyc_1;  
       end if; 
    end if;   
end process;
 
-- reset the crc error at the beginning of an event
-- calculated the crc of each channel's header and compare to that channel's declared crc
-- if a channel has an error, the crc_error (header_mismatch) will be set, and it will remain 
-- set until the next event is started.    The header_mismatch flag is incorporated into the event trailer
 
 
  
process (clock) begin
    if rising_edge (clock) then
       if (crc_reset = '1') then 
           crc_error <= '0';
       elsif (cyc_2 = '1') then
          if (CRC_out /= declared_crc_reg) then   
               crc_error  <= '1';
          else 
                 crc_error  <=  crc_error;
          end if;           
       end if;
    end if;
end process;         
 
header_mismatch <= crc_error;
 
end RTL;