RTL Architecture Reference

Processes
PROCESS_205	( pp_clock )
PROCESS_206	( pp_clock )
PROCESS_207	( pp_clock )
PROCESS_208	( pp_clock )
PROCESS_209	( pp_clock )

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
l1id_ttc_prior_0	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_ttc_prior_1	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_ttc_prior_2	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_ttc_prior_n	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_ttc_prior_m	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_ttc_after_0	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_ttc_after_1	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_ttc_after_2	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_ttc_mismatch	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_pkt_prior_0	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_pkt_prior_1	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_pkt_prior_2	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_pkt_after_0	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_pkt_after_1	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_pkt_after_2	STD_LOGIC_VECTOR ( 31 downto 0 )
l1id_pkt_mismatch	STD_LOGIC_VECTOR ( 31 downto 0 )
channel	STD_LOGIC_VECTOR ( 7 downto 0 )
post_capture	STD_LOGIC
postcapture_count	STD_LOGIC_VECTOR ( 1 downto 0 )
clear	std_logic
clear_s	std_logic
clear_s_del	std_logic
armed	std_logic
armed_s	std_logic
armed_s_del	std_logic
armed_pulse	std_logic
armed_stat	std_logic
l_header_marker	std_logic
l1id_capture_control	std_logic_vector ( 31 downto 0 )
tvalid_prev	std_logic
sample	std_logic
l1id_capture_status	std_logic_vector ( 31 downto 0 )
l1id_capture_control_reg_stb	std_logic
l1id_capture_control_reg_rst	std_logic
l1id_eq	std_logic
triggered	std_logic

Instantiations
fabric	ipbus_fabric_sel
l1id_capture_control_reg	ipbus_reg_v
l1id_capture_status_reg	ipbus_syncreg_v
pkt_miss_reg	ipbus_syncreg_v
ttc_miss_reg	ipbus_syncreg_v
ttc_last_reg	ipbus_syncreg_v
ttc_penultimate_reg	ipbus_syncreg_v

Detailed Description

Definition at line 60 of file l1id_capture.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/l1id_capture.vhd