l1id_capture.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.07.2022 13:53:05
-- Design Name: 
-- Module Name: l1id_capture - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
 
use work.ipbus.all;
use work.ipbus_decode_L1CaloHubRodL1idCaptureRegisters.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
 
 
--could this function be implemented within the "input_capture" block if TTC_l1ID was added to the registers? 
 
entity l1id_capture is
     generic (
        sim              : integer    := 0
        ); 
    Port ( 
           ipb_clk                  : in std_logic;
           ipb_rst                  : in std_logic;
           ipb_in                   : in ipb_wbus;
           ipb_out                  : out ipb_rbus;
           pp_clock                 : in STD_LOGIC;
           reset                    : in STD_LOGIC;
           s_tvalid                 : in STD_LOGIC;
           s_tlast                  : in STD_LOGIC;
           idle_state               : in STD_LOGIC;
           l1id_ttc                 : in STD_LOGIC_VECTOR(31 downto 0);
           l1id_pkt                 : in STD_LOGIC_VECTOR(31 downto 0);
           current_chan             : in STD_LOGIC_VECTOR(7 downto 0);     --allow any channel to mismatch, and then record that channel 
           first_chan               : in STD_LOGIC_VECTOR(4 downto 0);     --only capture the ttc_l1id on the first channel 
           poll_chan                : in STD_LOGIC
           );
end l1id_capture;
 
architecture RTL of l1id_capture is
 
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal l1id_ttc_prior_0             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_ttc_prior_1             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_ttc_prior_2             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_ttc_prior_n             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_ttc_prior_m             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_ttc_after_0             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_ttc_after_1             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_ttc_after_2             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_ttc_mismatch            : STD_LOGIC_VECTOR(31 downto 0);
 
signal l1id_pkt_prior_0             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_pkt_prior_1             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_pkt_prior_2             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_pkt_after_0             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_pkt_after_1             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_pkt_after_2             : STD_LOGIC_VECTOR(31 downto 0);
signal l1id_pkt_mismatch            : STD_LOGIC_VECTOR(31 downto 0);
signal channel                      : STD_LOGIC_VECTOR(7 downto 0);
signal post_capture                 : STD_LOGIC; 
signal postcapture_count            : STD_LOGIC_VECTOR(1 downto 0);
 
signal clear                   : std_logic;
signal clear_s                 : std_logic;
signal clear_s_del             : std_logic;
signal armed                   : std_logic;
signal armed_s                 : std_logic;
signal armed_s_del             : std_logic;
signal armed_pulse             : std_logic;
signal armed_stat              : std_logic;
signal l_header_marker         : std_logic;
signal l1id_capture_control    : std_logic_vector(31 downto 0);
signal tvalid_prev             : std_logic;
signal sample                  : std_logic;
signal l1id_capture_status     : std_logic_vector(31 downto 0);
signal l1id_capture_control_reg_stb : std_logic;
signal l1id_capture_control_reg_rst : std_logic;
signal l1id_eq                 : std_logic;
signal triggered               : std_logic;
 
--COMPONENT ila_l1icap
 
--PORT (
--  clk : IN STD_LOGIC;
--  probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
--  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
--  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
--  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
--  probe4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
--  probe5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
--);
--END COMPONENT  ;
 
begin
 
no_sim_regs: if SIM=0 generate 
fabric: entity work.ipbus_fabric_sel
  generic map(
    NSLV => N_SLAVES,
    SEL_WIDTH => IPBUS_SEL_WIDTH)
  port map(
   ipb_in => ipb_in,
   ipb_out => ipb_out,
 
    sel => ipbus_sel_L1CaloHubRodL1IDCaptureRegisters(ipb_in.ipb_addr),
    ipb_to_slaves => ipbw,
    ipb_from_slaves => ipbr
  );
 
 
 
--pulse reg for arming the capture mech -----
L1ID_Capture_Control_reg: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset => l1id_capture_control_reg_rst,
          ipbus_in => ipbw(N_SLV_L1ID_CAPTURE_CONTROL),
          ipbus_out => ipbr(N_SLV_L1ID_CAPTURE_CONTROL),
          stb(0) => l1id_capture_control_reg_stb,
          q(0) => l1id_capture_control
        );
l1id_capture_control_reg_rst <=  l1id_capture_control_reg_stb or ipb_rst;  
 
L1ID_Capture_status_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_L1ID_CAPTURE_STATUS),
          ipb_out => ipbr(N_SLV_L1ID_CAPTURE_STATUS),
          slv_clk => pp_clock,
          d(0) => l1id_capture_status,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
pkt_miss_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_PKT_MISS),
          ipb_out => ipbr(N_SLV_PKT_MISS),
          slv_clk => pp_clock,
          d(0) => l1id_pkt_mismatch,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
ttc_miss_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_MISS),
          ipb_out => ipbr(N_SLV_TTC_MISS),
          slv_clk => pp_clock,
          d(0) => l1id_ttc_mismatch,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
ttc_last_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_LAST),
          ipb_out => ipbr(N_SLV_TTC_LAST),
          slv_clk => pp_clock,
          d(0) => l1id_ttc_prior_n, --l1id_ttc_prior_0,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
ttc_penultimate_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_PENULTIMATE),
          ipb_out => ipbr(N_SLV_TTC_PENULTIMATE),
          slv_clk => pp_clock,
          d(0) => l1id_ttc_prior_m, --l1id_ttc_prior_1,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
end generate no_sim_regs; 
 
 
 
l1id_eq <= '1' when l1ID_ttc = l1ID_pkt else '0';
 
l1id_capture_status <= x"00000" & channel & "00" & triggered & armed_stat;
--sample <= idle_state and s_tvalid and l_header_marker; --sampling point to capture l1id, pkt, and equality --note that poll_chan could be used for this
sample <= poll_chan;
 
--both L1ID's are available at the time poll_chan is activated. 
 
-------sample the pulse reg in the pp_clock domain ------
--armed_s samples the pulse bit running on ipb_clk
--armed_s_del sample armed_s synchronously on pp_clock
--armed_stat is the user's status flag indicating the mech is armed, but not triggered
 
--clear <= l1id_capture_control(1);
 
--clear pulse happens on trailing edge of ipbus pulse 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     clear_s <= l1id_capture_control(1);
     clear_s_del <= clear_s; 
  end if;   
end process;
 
clear <= clear_s_del and not clear_s;
 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     armed_s <= l1id_capture_control(0);
     armed_s_del <= armed_s; 
  end if;   
end process;
 
armed_pulse <= armed_s_del and not armed_s;
 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     if (armed_pulse = '1') then
       armed_stat <= '1';
     elsif  (ipb_rst = '1') or (triggered = '1') or (clear = '1') or (reset = '1') then 
       armed_stat <= '0';         
     else 
       armed_stat <= armed_stat;     
     end if;  
  end if;
end process;
 
 
----The header marker coming from the TOB processor is not currently reliable, so a stand alone version is created here 
--process (pp_clock) begin
--    if rising_edge (pp_clock) then
--       if (ipb_rst = '1') or (clear = '1') then
--          tvalid_prev <= '0';
--       else
--          tvalid_prev <= (not s_tvalid) or (s_tlast and s_tvalid);
--       end if;
--    end if;
-- end process;
 
--l_header_marker <= s_tvalid and tvalid_prev and not s_tlast;  --packets should be at least two 64-bit words (header and trailer) 
 
 
 
 
 
 
 
process (pp_clock) begin
  if rising_edge (pp_clock) then 
     if (ipb_rst = '1') or (clear = '1') or (reset = '1') or (armed_pulse = '1') then
        triggered <= '0';
        l1id_pkt_mismatch <= (others=> '0');
        l1id_ttc_mismatch <= (others=> '0');
        channel <= (others=> '0');
     elsif (sample = '1') and (l1id_eq = '0') and (armed_stat = '1') then 
        channel <= current_chan;
        triggered <= '1';
        l1id_pkt_mismatch <= l1id_pkt;
        l1id_ttc_mismatch <= l1id_ttc;
        l1id_ttc_prior_n  <= l1id_ttc_prior_0;
        l1id_ttc_prior_m  <= l1id_ttc_prior_1;
     
     else 
        channel <= channel;  
        triggered <= triggered;
        l1id_pkt_mismatch <= l1id_pkt_mismatch;
        l1id_ttc_mismatch <= l1id_ttc_mismatch;
     end if; 
  end if; 
 end process;    
        
process (pp_clock) begin
  if rising_edge (pp_clock) then 
     if (ipb_rst = '1') or (clear = '1') or (reset = '1') then
        l1id_ttc_prior_0  <= (others=> '0');
        l1id_ttc_prior_1 <= (others=> '0');  
--     elsif (sample = '1') and (armed_stat = '1') and (l1id_ttc /= l1id_ttc_prior_0) then --and (l1id_eq = '1')
--     elsif (sample = '1') and (armed_stat = '1') and (current_chan = first_chan) then  --only update past l1ids when capturing the first channel l1id
     elsif (sample = '1') and (current_chan = first_chan) then  --update these hidden registers every time a new event is being processed on first_chan
        l1id_ttc_prior_0  <= l1id_ttc;
        l1id_ttc_prior_1 <= l1id_ttc_prior_0; 
     else 
         l1id_ttc_prior_0 <= l1id_ttc_prior_0;
         l1id_ttc_prior_1 <= l1id_ttc_prior_1; 
     end if; 
  end if;      
end process;
    
 
--l1id_capture_ila : ila_l1icap
--PORT MAP (
--  clk => pp_clock,
 
--  probe0(0) => armed_stat, 
--  probe1(0) => triggered, 
--  probe2(0) => sample, 
--  probe3(0) => l1id_eq, 
--  probe4 => l1id_ttc_prior_0,
--  probe5 => l1id_ttc_prior_1
--);
 
 
 
end RTL;