RTL Architecture Reference

Processes
PROCESS_262	( clock )

Signals
counter	std_logic_vector ( counter_width- 1 downto 0 ) := ( others = > ' 1 ' )
count_max	STD_LOGIC_VECTOR ( counter_width- 1 downto 0 )
pulse_out_i	std_logic := ' 0 '

Detailed Description

Definition at line 49 of file pulse_stretch.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/pulse_stretch.vhd