pulse_stretch.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.05.2019 13:13:43
-- Design Name: 
-- Module Name: pulse_stretch - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity pulse_stretch is
    generic (
 COUNTER_WIDTH  : integer :=   5       
   );    
    Port ( 
          clock : in STD_LOGIC;
          reset :  in STD_LOGIC;
          pulse_in : in STD_LOGIC;
          pulse_out : out STD_LOGIC
                   
          );
end pulse_stretch;
 
 
architecture RTL of pulse_stretch is
 
signal counter :  std_logic_vector(counter_width-1 downto 0) := (others => '1');
signal count_max : STD_LOGIC_VECTOR (counter_width-1 downto 0); --:= (others => '1');
signal pulse_out_i     : std_logic := '0';
 
 
begin
 
count_max <= (others => '1');
 
process (clock) begin 
  if rising_edge (clock) then 
    if reset = '1' then 
      counter <= (others=> '1');
      pulse_out_i <= '0';    
    elsif pulse_in = '1' then
      counter <= (others=> '0');
      pulse_out_i <= '1';
    elsif counter = count_max then 
      pulse_out_i <= '0';
      counter <= counter; 
    else 
      counter <= counter + 1;
    end if; 
  end if; 
end process;            
      
pulse_out <=  pulse_out_i or pulse_in;      
 
 
end RTL;