self_reset Entity Reference

The clock input is connected to the 125MHz ethernet clock. A Gap width of 17-bits therefore equates to (2**17) * (1/125E6) = 1.05mS A Gap width of 20-bits equates to 8.39mS. More...

Inheritance diagram for self_reset:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_UNSIGNED

Generics
GAP_WIDTH	integer := 17
jfex	integer := 0

Ports
clock	in	STD_LOGIC
channel_up	in	STD_LOGIC
reset_in	in	STD_LOGIC
aurora_reset	in	STD_LOGIC
error_counter_reset	in	STD_LOGIC
channel_down_auto_reset_disable	in	STD_LOGIC
reset_out	out	std_logic
reset_count	out	std_logic_vector ( 31 downto 0 )
chan_up_time	out	std_logic_vector ( 31 downto 0 )

Detailed Description

The clock input is connected to the 125MHz ethernet clock. A Gap width of 17-bits therefore equates to (2**17) * (1/125E6) = 1.05mS A Gap width of 20-bits equates to 8.39mS.

the Self reset block is used to reset aurora channels which have gone down or are failing to come up. There is a "GAP width" generic which is used determine how much time the circuit will wait for the channel to come up before applying another reset pulse. The reset from this curcuit is sent both to the ROD Rx reset timer and to the Readout Control output. The Hub places the reset into the Combined TTC channel where it is picked up by the FEX. The should then trigger its own Aurora reset timer.

Definition at line 47 of file self_reset.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/self_reset.vhd