self_reset.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 18.01.2019 16:38:54
-- Design Name: 
-- Module Name: self_reset - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
 
 
 
entity self_reset is
  generic
    (            
            GAP_WIDTH   : integer :=   17;       -- width of gap counter ex; 5 makes gap of 32 cycles 
            jfex        : integer :=   0  
    );  
    Port ( 
            clock : in STD_LOGIC;
            channel_up :  in STD_LOGIC;
            reset_in   : in STD_LOGIC;       --must be the OR of other reset sources 
            aurora_reset : in STD_LOGIC;
            error_counter_reset: in STD_LOGIC;
            channel_down_auto_reset_disable : in STD_LOGIC;
            reset_out   : out std_logic;
            reset_count : out std_logic_vector(31 downto 0);
            chan_up_time : out std_logic_vector(31 downto 0)          
            );
end self_reset;
 
architecture RTL of self_reset is
 
    
       
 
COMPONENT ila_self_reset
 
PORT (
    clk : IN STD_LOGIC;
    probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe5 : IN STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END COMPONENT  ;
 
 
signal  channel_up_delay : std_logic;
--signal  start_waiting : std_logic; 
signal reset_pulse   : std_logic := '0';
signal  gap_count  : STD_LOGIC_VECTOR (GAP_WIDTH-1 downto 0) := (others => '0');
signal gap_limit : STD_LOGIC_VECTOR (GAP_WIDTH-1 downto 0) := (others => '1');
signal reset_pulse2 : std_logic := '0';
signal reset_pulse3 : std_logic := '0';
signal reset_count_i : STD_LOGIC_VECTOR (31 downto 0);
signal chan_up_timer : STD_LOGIC_VECTOR (31 downto 0);
 
begin
 
 
gap_limit <= (others => '1');
 
--detect falling channel_up   link goes down
-- when detected, start waiting is a pulse that starts the delay timer. 
 
process (clock) begin
        if rising_edge(clock) then 
            if (channel_down_auto_reset_disable = '0') and ((channel_up_delay = '1' and channel_up = '0') or (channel_up = '0' and (gap_count = gap_limit)))  then 
                    reset_pulse <= '1';
            elsif reset_pulse = '1' or reset_in = '1' then 
                  reset_pulse  <= '0';
            else 
                  reset_pulse <= reset_pulse;
            end if; 
        end if; 
end process;   
 
process (clock) begin
        if rising_edge(clock) then 
              reset_pulse2 <= reset_pulse; 
              reset_pulse3 <= reset_pulse2; 
        end if;
        
end process; 
 
               
                   
                       
                  
 process (clock) begin
        if rising_edge(clock) then
            channel_up_delay <= channel_up; 
        end if; 
 end process; 
 
            
                                       
--gap count 
 process (clock) begin 
   if rising_edge (clock) then 
     if (reset_in = '1') or (aurora_reset = '1') or (channel_up = '1')then 
       gap_count <= (others => '0');
     elsif (reset_in = '0') and (channel_up = '0') and (aurora_reset = '0')  then 
       gap_count <= gap_count+1;  
     else gap_count <= gap_count;  
     end if; 
   end if; 
 end process;      
 
 
 --count the number of Aurora Resets 
  process (clock) begin 
   if rising_edge (clock) then 
     if (reset_in = '1') or (error_counter_reset = '1') then 
       reset_count_i <= (others => '0');
     elsif (reset_pulse2 = '1') then
        reset_count_i <= (reset_count_i + 1); 
     else
        reset_count_i <= reset_count_i;
     end if;
   end if;        
  end process;
  
  reset_count <= reset_count_i;
 
 ------measure aurora reset time: reset falling to channel_up rising     (this is for checking jfex) 
 
 process (clock) begin 
  if rising_edge (clock) then 
    if (aurora_reset = '1')  then 
      chan_up_timer <= (others => '0');       
    elsif (channel_up = '1')  then
      chan_up_timer <= chan_up_timer;
    else
      chan_up_timer <= chan_up_timer +1;           
    end if; 
  end if; 
end process;      
chan_up_time <= chan_up_timer;
 
        
--temporarily disable auto reset --------------------
--now re-enabled 25/01/2021
 
--kill_rst: if jfex =1 generate 
--  reset_out  <=  reset_in;
--end generate kill_rst;
 
--slf_rst: if jfex =0 generate
  reset_out  <= reset_pulse2 or reset_pulse3 or reset_in; 
--end generate slf_rst; 
 
 
--ila_self_rst: ila_self_reset 
--port map (
--  clk       => clock,
--  probe0(0) => channel_up,
--  probe1(0) => aurora_reset,
--  probe2(0) => reset_pulse2,
--  probe3(0) => reset_pulse3,
--  probe4(0) => reset_in,
----  probe5(19 downto 17)    => "000",
--  probe5(19 downto 0) => gap_count 
--);
 
 
 
end RTL;