trailer_map Entity Reference

Inheritance diagram for trailer_map:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Generics
jfex	integer := 1

Ports
pp_clock	in	STD_LOGIC
reset	in	STD_LOGIC
current_chan	in	STD_LOGIC_VECTOR ( 4 downto 0 )
chan_len_error	in	STD_LOGIC
chan_hdr_crc_err	in	STD_LOGIC
chan_crc20_err	in	STD_LOGIC
L1ID_eq	in	STD_LOGIC
chan_crc20_samp	in	STD_LOGIC
crc9_err_samp	in	STD_LOGIC
len_err_samp	in	STD_LOGIC
L1ID_eq_samp	in	STD_LOGIC
timeout_error	in	STD_LOGIC
clear_map	in	STD_LOGIC
sel_corr_trailer	in	STD_LOGIC
error_map	out	STD_LOGIC_VECTOR ( 11 downto 0 )
lmem	out	STD_LOGIC_VECTOR ( 3 downto 0 )
rod_err_map	out	STD_LOGIC_VECTOR ( 6 downto 0 )
debug_pkt_module_map	out	STD_LOGIC_VECTOR ( 11 downto 0 )

Detailed Description

Definition at line 34 of file trailer_map.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/trailer_map.vhd