trailer_map.vhd

----------------------------------------------------------------------------------
-- Company:  University of Cambridge 
-- Engineer: Ed Flaherty 
-- 
-- Create Date: 15.02.2020 12:57:20
-- Design Name: 
-- Module Name: trailer_map - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity trailer_map is
    generic (
            jfex                  : integer   := 1
            );         
    Port ( 
        pp_clock            : in STD_LOGIC;
        reset               : in STD_LOGIC;
        current_chan        : in STD_LOGIC_VECTOR (4 downto 0);
        chan_len_error      : in STD_LOGIC;
        chan_hdr_crc_err    : in STD_LOGIC;
        chan_crc20_err      : in STD_LOGIC;
        L1ID_eq             : in STD_LOGIC;
        chan_crc20_samp     : in STD_LOGIC; 
        crc9_err_samp       : in STD_LOGIC;
        len_err_samp        : in STD_LOGIC;
        L1ID_eq_samp        : in STD_LOGIC; 
        timeout_error       : in STD_LOGIC;
        clear_map           : in STD_LOGIC;
        sel_corr_trailer    : in STD_LOGIC;
        error_map           : out STD_LOGIC_VECTOR(11 downto 0);
        lmem                : out STD_LOGIC_VECTOR(3 downto 0);
        rod_err_map         : out STD_LOGIC_VECTOR(6 downto 0);
        debug_pkt_module_map: out STD_LOGIC_VECTOR(11 downto 0)
                       
        );
end trailer_map;
 
architecture RTL of trailer_map is
 
component onehot_dec is 
 
    generic(
           n       : integer :=   4;
           m       : integer :=   16
          );
     Port ( 
          bin_in : in STD_LOGIC_VECTOR (n-1 downto 0);
          oh_out : out STD_LOGIC_VECTOR (m-1 downto 0));
 
end component;
 
signal error_map_reg  :  STD_LOGIC_VECTOR(11 downto 0);
signal chan_sel       :  STD_LOGIC_VECTOR(15 downto 0);
signal crc20_err      :  STD_LOGIC;
signal len_err        :  STD_LOGIC;
signal crc9_err       :  STD_LOGIC;
signal L1id_err       :  STD_LOGIC;
signal any_err        :  STD_LOGIC;
 
signal lmem_reg      :  STD_LOGIC_VECTOR(3 downto 0);
 
signal chan_in       :  STD_LOGIC_VECTOR (3 downto 0);
signal module_in     :  STD_LOGIC_VECTOR (3 downto 0);
signal module_sel    :  STD_LOGIC_VECTOR(15 downto 0);
 
signal current_chan_del :  STD_LOGIC_VECTOR (4 downto 0);
signal crc20_reg        :  STD_LOGIC;
signal len_err_reg      :  STD_LOGIC;
signal crc9_reg         :  STD_LOGIC;
signal L1id_err_reg     :  STD_LOGIC;
signal timeout_err_reg  :  STD_LOGIC;
signal flag          :  STD_LOGIC_VECTOR(11 downto 0);
signal lflag          :  STD_LOGIC_VECTOR(3 downto 0);
signal corr_trailer_flag :  STD_LOGIC;
 
begin
 
 
crc20_err <= chan_crc20_err and chan_crc20_samp;
len_err   <= chan_len_error and len_err_samp;
crc9_err  <= chan_hdr_crc_err and crc9_err_samp;
L1id_err  <= L1id_eq_samp and not L1id_eq; 
any_err   <= crc9_err or len_err or crc20_err or L1id_err;
 
process (pp_clock) begin
  if rising_edge (pp_clock) then
     current_chan_del <= current_chan;  
   end if;
end process;
 
------------------------------------------
---- ROD ERROR MAP -------------------------
------------------------------------------
 
--FEX timeout Error 
process (pp_clock) begin
  if rising_edge (pp_clock) then
    if (reset = '1') or (clear_map = '1') then
      timeout_err_reg <= '0';
    elsif (timeout_error = '1') then 
      timeout_err_reg <= '1';
    else
      timeout_err_reg <= timeout_err_reg;  
    end if;
  end if; 
end process;
rod_err_map(0) <= timeout_err_reg;
 
 
 
--Header Mismatch 
process (pp_clock) begin
  if rising_edge (pp_clock) then
    if (reset = '1') or (clear_map = '1') then
      L1id_err_reg <= '0';
    elsif (L1id_err = '1') then 
      L1id_err_reg <= '1';
    else
      L1id_err_reg <= L1id_err_reg;  
    end if;
  end if; 
end process;
rod_err_map(1) <= L1id_err_reg;
 
-- Length Mismatch 
process (pp_clock) begin
  if rising_edge (pp_clock) then
    if (reset = '1') or (clear_map = '1') then
      len_err_reg <= '0';
    elsif (len_err = '1') then 
      len_err_reg <= '1';
    else
      len_err_reg <= len_err_reg;  
    end if;
  end if; 
end process; 
--rod_err_map(2) <= len_err_reg;
--note that len_err has been or'd with len_err_reg in order to produce the flag one cycle early
--this allows an error in the last event fragment to be propagated to the event trailer crc20 calculation one cycle early 
rod_err_map(2) <= len_err_reg or len_err; 
 
--protocol error-- this is an OR of all of the Aurora errors to be passed through as a tuser 
rod_err_map(3) <= '0';
 
 
--Header CRC error crc9_err
process (pp_clock) begin
  if rising_edge (pp_clock) then
    if (reset = '1') or (clear_map = '1') then
      crc9_reg <= '0';
    elsif (crc9_err = '1') then 
      crc9_reg <= '1';
    else
       crc9_reg <= crc9_reg;  
    end if;
  end if; 
end process; 
--rod_err_map(4) <= crc9_reg;
--note that crc9_err has been or'd with len_err_reg in order to produce the flag one cycle early
--this allows an error in the last event fragment to be propagated to the event trailer crc20 calculation one cycle early 
rod_err_map(4) <= crc9_reg or crc9_err;
 
--Payload CRC error 
process (pp_clock) begin
  if rising_edge (pp_clock) then
    if (reset = '1') or (clear_map = '1') then
      crc20_reg <= '0';
    elsif (crc20_err = '1') then 
      crc20_reg <= '1';
    else
       crc20_reg <= crc20_reg;  
    end if;
  end if; 
end process; 
 
--rod_err_map(5) <= crc20_reg;
--note that crc20_err has been or'd with len_err_reg in order to produce the flag one cycle early
--this allows an error in the last event fragment to be propagated to the event trailer crc20 calculation one cycle early 
rod_err_map(5) <= crc20_reg or crc20_err;     
 
 
-----------------------------------------------------------------------------------
--corrective trailer flag 
process (pp_clock) begin
    if rising_edge (pp_clock) then
         if (reset = '1') or (clear_map = '1')  then 
             corr_trailer_flag <= '0';
         elsif (sel_corr_trailer    = '1') then  
             corr_trailer_flag <= '1';
         else 
             corr_trailer_flag <= corr_trailer_flag;    
         end if; 
     end if; 
end process;
--Corrective Trailer 
--rod_err_map(6) <= corr_trailer_flag or sel_corr_trailer;
rod_err_map(6) <= '0';
-----------------------------------------------------efex-specific-source-module-error-map---------------------------------------------------
 
 
gen_efex_map: if jfex=0 generate
 
chan_selector: onehot_dec
  port map (
   bin_in => current_chan_del(3 downto 0),
   oh_out => chan_sel
  ); 
  
debug_pkt_module_map <= chan_sel(11 downto 0);
 
process (pp_clock) begin
  if rising_edge (pp_clock) then
 --   if reset = '1' then
 --   if (reset = '1') or (clear_map = '1') then
    if  (clear_map = '1') then
      error_map_reg <= (others => '0');
    else  
       for I in 0 to 11 loop
--        if ((chan_sel(I) = '1') and (any_err = '1') ) then  --need to factor chan enable here to avoid errors from off channels?
          if ((flag(I) = '1') ) then  --need to factor chan enable here to avoid errors from off channels?        
             error_map_reg(I) <= '1';
          end if;
       end loop;
    end if;   
  end if;
end process;
 
process(chan_sel, any_err) begin
  for K in 0 to 11 loop
    flag(K) <= chan_sel(K) and any_err;
  end loop;
end process;  
 
process(error_map_reg, flag) begin
  for K in 0 to 11 loop
    error_map(K) <= error_map_reg(K) or flag(K);
  end loop;
end process;  
 
 
--error_map  <= error_map_reg;
lmem <= (others => '0');
 
end generate gen_efex_map;
-----------------------------------------------------jfex-specific--source-module-error-map-----------------------------------------------------------
gen_jfex_map: if jfex=1 generate
chan_selector: onehot_dec
  port map (
   bin_in => chan_in(3 downto 0),
   oh_out => chan_sel
  ); 
 
debug_pkt_module_map <= chan_sel(11 downto 0);
chan_in <= "00" & current_chan_del(1 downto 0); 
 
module_selector: onehot_dec
  port map (
   bin_in => module_in,
   oh_out => module_sel
  ); 
 
module_in <= "0" & current_chan_del(4 downto 2); 
 
---set the link map: lmem 
process (pp_clock) begin
  if rising_edge (pp_clock) then
    if reset = '1' then
      lmem_reg <= (others => '0');
    else  
       for I in 0 to 3 loop
--        if ((chan_sel(I) = '1') and (any_err = '1') ) then
          if ((lflag(I) = '1') ) then
             lmem_reg(I) <= '1';
          end if;
       end loop;
    end if;   
  end if;
end process;
 
process(chan_sel, any_err) begin
  for K in 0 to 3 loop
    lflag(K) <= chan_sel(K) and any_err;
  end loop;
end process;
 
--process(error_map_reg, flag) begin
process(error_map_reg, flag, lmem_reg, lflag) begin
  for K in 0 to 3 loop
    lmem(K) <= lmem_reg(K) or lflag(K);
  end loop;
end process;  
--lmem  <= lmem_reg(3 downto 0);
 
 
--set the module error map 
 
process (pp_clock) begin
  if rising_edge (pp_clock) then
    if reset = '1' then
      error_map_reg <= (others => '0');
    else  
       for J in 0 to 5 loop
--        if ((module_sel(J) = '1') and (any_err = '1') ) then
          if ((flag(J) = '1')) then
               error_map_reg(J) <= '1';
          end if;
       end loop;
    end if;   
  end if;
end process;
 
process(module_sel, any_err) begin
  for K in 0 to 5 loop
    flag(K) <= module_sel(K) and any_err;
  end loop;
end process;  
 
process(module_sel, any_err) begin
  for K in 6 to 11 loop
    flag(K) <= '0';
  end loop;
end process;  
 
process(error_map_reg, flag) begin
  for K in 0 to 5 loop
    error_map(K) <= error_map_reg(K) or flag(K);
  end loop;
end process;  
 
process(error_map_reg, flag) begin
  for K in 6 to 11 loop
    error_map(K) <= error_map_reg(K);
  end loop;
end process;  
--error_map  <= error_map_reg;
 
end generate gen_jfex_map;
 
end RTL;