RTL Architecture Reference

Processes
PROCESS_320	( cttc_user_clk )
PROCESS_321	( cttc_user_clk )
PROCESS_322	( cttc_user_clk , reset , event_count_reset )
PROCESS_323	( cttc_user_clk )
PROCESS_324	( cttc_user_clk )
PROCESS_325	( cttc_user_clk )
PROCESS_326	( cttc_user_clk )
PROCESS_327	( event_sel( 1 ) , event_sel( 0 ) , rod_slot , L1ID( 0 ) )
	The rod_slot bit is set to '1' for the HUB in logical slot 1 and to '0' for the HUB in logical slot 2.
PROCESS_328	( pp_clk )

Components
ttc_header_fifo
osum_crc9d32	<Entity osum_crc9d32>
l1id_cont_check	<Entity l1id_cont_check>
ila_ttc_in
ila_ttc_out
ila_bulk_ttc

Signals
version	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
L1A_delay	STD_LOGIC
L1A_delay_2	STD_LOGIC
BCR	STD_LOGIC
BCR_delay	STD_LOGIC
ECR	STD_LOGIC
trig_type	STD_LOGIC
L1ID	STD_LOGIC_VECTOR ( 23 DOWNTO 0 )
link_reset	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
ROD_busy	STD_LOGIC
link_enable	STD_LOGIC
shelf_num	STD_LOGIC_VECTOR ( 2 DOWNTO 0 )
crc	STD_LOGIC_VECTOR ( 8 DOWNTO 0 )
BCN	STD_LOGIC_VECTOR ( 11 DOWNTO 0 )
BCN_count	STD_LOGIC_VECTOR ( 11 DOWNTO 0 )
Event_Counter	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
Orbit	STD_LOGIC_VECTOR ( 15 DOWNTO 0 )
header_fifo_wen	STD_LOGIC
dset_header_fifo_wen	STD_LOGIC
ttc_crc_ok	STD_LOGIC
ECR_delay	STD_LOGIC
ECRID	STD_LOGIC_VECTOR ( 7 DOWNTO 0 )
cttc_word	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
crc_start	STD_LOGIC
crc_gen	STD_LOGIC_VECTOR ( 8 DOWNTO 0 )
L1ID_32	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
ttc_fifo_valid	STD_LOGIC
header_fifo_empty_i	STD_LOGIC
master_header_i	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
header_fifo_level_i	STD_LOGIC_VECTOR ( 8 DOWNTO 0 )
header_fifo_full_i	STD_LOGIC
bulk_ttc_fifo_valid	STD_LOGIC
bulk_header_fifo_empty_i	STD_LOGIC
ttc_reg_i	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
proposed_crc	STD_LOGIC_VECTOR ( 8 DOWNTO 0 )
fifo_reset	STD_LOGIC
event_en	STD_LOGIC
bulk_fifo_count	STD_LOGIC_VECTOR ( 8 DOWNTO 0 )
bulk_header_fifo_full_i	STD_LOGIC
bulk_master_header_i	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
bulk_header_fifo_underflow	STD_LOGIC
crc_word_0	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
crc_word_3	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
flx_bp_sync_0	STD_LOGIC_VECTOR ( 11 DOWNTO 0 )
flx_bp_sync_1	STD_LOGIC_VECTOR ( 11 DOWNTO 0 )

Attributes
async_reg	string
async_reg	signal is " true "
dont_touch	string
dont_touch	signal is " true "

Instantiations
ttc_fifo	ttc_header_fifo
bulk_ttc_fifo	ttc_header_fifo
ila_bulk_ttc_fifo	ila_bulk_ttc
cttc_crc	osum_crc9d32 <Entity osum_crc9d32>
ila_ttc_fifo_in	ila_ttc_in
ila_ttc_fifo_out	ila_ttc_out
l1id_continuity_checker	l1id_cont_check <Entity l1id_cont_check>

Detailed Description

Definition at line 109 of file ttc_info.vhd.

Member Function Documentation

PROCESS_322()

PROCESS_322 (   cttc_user_clk ,   reset ,   event_count_reset   )

Process

Event Counter: The Event counter is a local 32-bit counter that increments each L1A.
It is reset to '-1' on ECR. it is asynchronously set to "000" on reset

Definition at line 374 of file ttc_info.vhd.

Member Data Documentation

ila_ttc_fifo_in

ila_ttc_fifo_in ila_ttc_in

Instantiation

PING PONG EVENT SELECTOR

event_sel(1)	event_sel(0)	slot	Action	Usage
0	0	0	Accept event when ROD slot=L1ID(0)	default ping pong
0	1	0	Accept event when ROD slot= not L1ID(0)	opposite ping pong
0	0	1	Accept event when ROD slot=L1ID(0)	default ping pong
0	1	1	Accept event when ROD slot= not L1ID(0)	opposite ping pong
1	0	X	Accept no events	debug
1	1	X	Accept all events	Only One ROD in use

Definition at line 648 of file ttc_info.vhd.

---

The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/ttc_info.vhd