ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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ttc_info.vhd
1 
2 
3 ----------------------------------------------------------------------------------
4 -- Company: University of Cambridge
5 -- Engineer: Ed Flaherty
6 --
7 -- Create Date: 10.01.2018 14:40:41
8 -- Design Name:
9 -- Module Name: ttc_info - RTL
10 -- Project Name:
11 -- Target Devices:
12 -- Tool Versions:
13 -- Description:
14 --
15 -- Dependencies:
16 --
17 -- Revision:
18 -- Revision 0.01 - File Created
19 -- Additional Comments:
20 -- clock cycles
21 -- 1 seq = 01
22 -- ttc_word_0 load
23 -- 2 seq = 10
24 -- ttc_word_0 delay load
25 -- ttc_word_1 load
26 -- 3 seq = 11
27 -- ttc_word_2 load
28 -- 4 seq = 00
29 -- crc out reg load
30 -- comp crc
31 -- 5 seq = 00
32 -- fifo load (when L1A taken from word_0_delay = 1)
33 
34 
35 ----------------------------------------------------------------------------------
36 
37 
38 library IEEE;
39 use IEEE.STD_LOGIC_1164.ALL;
40 
41 -- Uncomment the following library declaration if using
42 -- arithmetic functions with Signed or Unsigned values
43 use IEEE.NUMERIC_STD.ALL;
44 use ieee.std_logic_unsigned.all;
45 
46 -- Uncomment the following library declaration if instantiating
47 -- any Xilinx leaf cells in this code.
48 --library UNISIM;
49 --use UNISIM.VComponents.all;
50 
51 entity ttc_info is
52  Port (
53  reset : in STD_LOGIC; --synchronous to lhc_clk
54  pp_clk : in STD_LOGIC;
55  cttc_user_clk : in STD_LOGIC;
56  seq : in STD_LOGIC_VECTOR (1 downto 0);
57 -- ttc_valid : in STD_LOGIC; --derived from seq statemachine - it would be possible toprovide a strobe for each word
58  ttc_word_0 : in STD_LOGIC_VECTOR (31 downto 0); --synchronous to cttc_user_clk
59  ttc_word_1 : in STD_LOGIC_VECTOR (31 downto 0); --synchronous to cttc_user_clk
60  ttc_word_2 : in STD_LOGIC_VECTOR (31 downto 0); --synchronous to cttc_user_clk
61  ttc_word_3 : in STD_LOGIC_VECTOR (31 downto 0); --synchronous to cttc_user_clk
62 
63  L1ID_error : out STD_LOGIC;
64  CTTC_CRC_error : out STD_LOGIC;
65  TTC_CRC_ignore : in std_logic;
66  TTC_fifo_rst : in STD_LOGIC;
67  header_read_en : in STD_LOGIC;
68  header_fifo_valid : out STD_LOGIC;
69  header_fifo_full : out STD_LOGIC;
70  header_fifo_empty : out STD_LOGIC;
71  header_fifo_level : out STD_LOGIC_VECTOR (8 downto 0);
72  master_header : out STD_LOGIC_VECTOR (63 downto 0); --synchronous to packet processor clk pp_clk
73 
74  bulk_L1ID_error : out STD_LOGIC;
75  bulk_CTTC_CRC_error : out STD_LOGIC;
76  bulk_header_read_en : in STD_LOGIC;
77  bulk_header_fifo_valid : out STD_LOGIC;
78  bulk_header_fifo_full : out STD_LOGIC;
79  bulk_header_fifo_empty : out STD_LOGIC;
80  bulk_header_fifo_level : out STD_LOGIC_VECTOR (8 downto 0);
81  bulk_master_header : out STD_LOGIC_VECTOR (63 downto 0);
82 
83  event_sel : in STD_LOGIC_VECTOR (1 downto 0);
84  rod_slot : in std_logic;
85 
86  ttc_reg : out STD_LOGIC_VECTOR(63 DOWNTO 0);
87  L1A : out STD_LOGIC;
88  L1A_delay_out : out STD_LOGIC;
89  l1id_mis_stretch : in std_logic;
90  event_count : out STD_LOGIC_VECTOR(31 DOWNTO 0);
91  orbit_count : out STD_LOGIC_VECTOR(15 DOWNTO 0);
92  event_count_reset : in std_logic;
93  orbit_count_reset : in std_logic;
94 
95  flx_backpressure : out STD_LOGIC_VECTOR(11 DOWNTO 0);
96  bcn_adjustment : in STD_LOGIC_VECTOR(11 DOWNTO 0);
97 
98  timeout_threshold : in STD_LOGIC_vector(31 downto 0);
99  l1id_continuity_control : in STD_LOGIC_vector (31 downto 0);
100  l1id_continuity_status : out STD_LOGIC_vector (31 downto 0);
101  l1id_local_miss : out STD_LOGIC_vector (31 downto 0);
102  l1id_ttc_miss : out STD_LOGIC_vector (31 downto 0);
103  l1id_error_count : out STD_LOGIC_vector(31 downto 0);
104  repeat_counter : out STD_LOGIC_vector(31 downto 0)
105 
106  );
107 end ttc_info;
108 
109 architecture RTL of ttc_info is
110 
111 
112 --TTC header fifo
113 --input from CTTC registers in the bit order required for the ROD output header
114 --inputs are synchronous to the CTTC Rx clock, and outputs are synchronous to the pp_clk (packet processor clock)
115 
116 COMPONENT ttc_header_fifo
117  PORT (
118  rst : IN STD_LOGIC;
119  wr_clk : IN STD_LOGIC;
120  rd_clk : IN STD_LOGIC;
121  din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
122  wr_en : IN STD_LOGIC;
123  rd_en : IN STD_LOGIC;
124  dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
125  full : OUT STD_LOGIC;
126  almost_full : OUT STD_LOGIC;
127  empty : OUT STD_LOGIC;
128  underflow : OUT STD_LOGIC;
129  valid : OUT STD_LOGIC;
130  rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
131  );
132 END COMPONENT;
133 
134 component osum_crc9d32
135  port(
136  clock : in std_logic;
137 
138  crc_start : in std_logic;
139  d_in : in std_logic_vector(31 downto 0);
140 
141  crc_out : out std_logic_vector(8 downto 0));
142 
143 end component;
144 
145 component l1id_cont_check
146  Port (
147 
148  clock : in STD_LOGIC;
149  reset : in STD_LOGIC;
150  -- clr_errors : in STD_LOGIC;
151  L1A : in STD_LOGIC;
152  ECR : in STD_LOGIC;
153  L1id : in STD_LOGIC_vector(23 downto 0);
154  ECRid : in STD_LOGIC_vector(7 downto 0);
155  timeout_threshold : in STD_LOGIC_vector(31 downto 0);
156  l1id_continuity_control : in STD_LOGIC_vector (31 downto 0);
157  l1id_continuity_status : out STD_LOGIC_vector (31 downto 0);
158  l1id_local_miss : out STD_LOGIC_vector (31 downto 0);
159  l1id_ttc_miss : out STD_LOGIC_vector (31 downto 0);
160  l1id_error_count : out STD_LOGIC_vector(31 downto 0);
161  repeat_counter : out STD_LOGIC_vector(31 downto 0)
162 
163 
164 
165  );
166 end component;
167 
168 COMPONENT ila_ttc_in
169 
170 PORT (
171  clk : IN STD_LOGIC;
172 
173  probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
174  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
175  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
176  probe3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
177  probe4 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
178  probe5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
179  probe6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
180  probe7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --word-0
181  probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --word-1
182  probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --word-2
183  probe10 :IN STD_LOGIC_VECTOR(31 DOWNTO 0); --word-3
184 
185  probe11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
186  probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
187  probe13: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
188  probe14: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
189  probe15: IN STD_LOGIC_VECTOR(0 DOWNTO 0);
190  probe16: IN STD_LOGIC_VECTOR(0 DOWNTO 0)
191 
192 );
193 END COMPONENT ;
194 
195 COMPONENT ila_ttc_out
196 
197 PORT (
198  clk : IN STD_LOGIC;
199  probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
200  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
201  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
202  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
203  probe4 : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
204  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
205  probe6 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
206  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
207 );
208 END COMPONENT ;
209 
210 component ila_bulk_ttc
211 port (
212  clk : IN STD_LOGIC;
213  probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); --2
214  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
215  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
216  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
217  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
218  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
219  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
220  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
221  probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
222  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
223  probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
224  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --1
225  probe12 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); --9
226  probe13 : IN STD_LOGIC_VECTOR(23 DOWNTO 0) --24
227 );
228 END COMPONENT ;
229 
230 
231 signal version : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 --signal L1A_out : STD_LOGIC;
233 signal L1A_delay : STD_LOGIC;
234 signal L1A_delay_2 : STD_LOGIC;
235 signal BCR : STD_LOGIC;
236 signal BCR_delay : STD_LOGIC;
237 signal ECR : STD_LOGIC;
238 signal trig_type : STD_LOGIC;
239 
240 signal L1ID : STD_LOGIC_VECTOR(23 DOWNTO 0);
241 signal link_reset : STD_LOGIC_VECTOR(3 DOWNTO 0);
242 signal ROD_busy : STD_LOGIC;
243 signal link_enable : STD_LOGIC;
244 signal shelf_num : STD_LOGIC_VECTOR(2 DOWNTO 0);
245 
246 signal crc : STD_LOGIC_VECTOR(8 DOWNTO 0);
247 signal BCN : STD_LOGIC_VECTOR(11 DOWNTO 0);
248 signal BCN_count : STD_LOGIC_VECTOR(11 DOWNTO 0);
249 signal Event_Counter : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 
251 signal Orbit : STD_LOGIC_VECTOR(15 DOWNTO 0);
252 signal header_fifo_wen : STD_LOGIC;
253 signal dset_header_fifo_wen : STD_LOGIC;
254 signal ttc_crc_ok : STD_LOGIC;
255 signal ECR_delay : STD_LOGIC;
256 signal ECRID : STD_LOGIC_VECTOR(7 DOWNTO 0);
257 signal cttc_word : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 signal crc_start : STD_LOGIC;
259 signal crc_gen : STD_LOGIC_VECTOR(8 DOWNTO 0);
260 signal L1ID_32 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 --signal ttc_word_0_delay : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 signal ttc_fifo_valid : STD_LOGIC;
263 signal header_fifo_empty_i : STD_LOGIC;
264 
265 signal master_header_i : STD_LOGIC_VECTOR(63 DOWNTO 0);
266 signal header_fifo_level_i : STD_LOGIC_VECTOR(8 DOWNTO 0);
267 signal header_fifo_full_i : STD_LOGIC;
268 
269 signal bulk_ttc_fifo_valid : STD_LOGIC;
270 signal bulk_header_fifo_empty_i : STD_LOGIC;
271 
272 signal ttc_reg_i : STD_LOGIC_VECTOR(63 DOWNTO 0);
273 
274 signal proposed_crc : STD_LOGIC_VECTOR(8 DOWNTO 0);
275 signal fifo_reset : STD_LOGIC;
276 signal event_en : STD_LOGIC;
277 
278 signal bulk_fifo_count : STD_LOGIC_VECTOR(8 DOWNTO 0);
279 signal bulk_header_fifo_full_i : STD_LOGIC;
280 signal bulk_master_header_i : STD_LOGIC_VECTOR(63 DOWNTO 0);
281 signal bulk_header_fifo_underflow : STD_LOGIC;
282 signal crc_word_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
283 signal crc_word_3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
284 
285 signal flx_bp_sync_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
286 signal flx_bp_sync_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
287 
288 attribute async_reg : string;
289 attribute async_reg of flx_bp_sync_0 : signal is "true";
290 attribute async_reg of flx_bp_sync_1 : signal is "true";
291 attribute dont_touch : string;
292 attribute dont_touch of flx_bp_sync_0 : signal is "true";
293 attribute dont_touch of flx_bp_sync_1 : signal is "true";
294 
295 
296 begin
297 
298 version(3 downto 0) <= ttc_word_0(11 downto 8);
299 L1A <= ttc_word_0(16);
300 BCR <= ttc_word_0(17);
301 ECR <= ttc_word_0(18);
302 --trig_type <= ttc_word_0(18);
303 L1ID <= ttc_word_1(23 downto 0);
304 ECRID <= ttc_word_1(31 downto 24);
305 L1ID_32 <= ttc_word_1;
306 link_reset <= ttc_word_3(3 downto 0);
307 ROD_busy <= ttc_word_3(4);
308 link_enable <= ttc_word_3(4);
309 shelf_num <= ttc_word_3(22 downto 20);
310 proposed_crc <= ttc_word_3(31 downto 23);
311 
312 process (cttc_user_clk) begin
313  if rising_edge (cttc_user_clk) then
314  if (reset ='1') then
315  L1A_delay <= '0';
316  L1A_delay_2 <= '0';
317  BCR_delay <= '0';
318  else
319  L1A_delay <= L1A;
320  L1A_delay_2 <= L1A_delay;
321  BCR_delay <= BCR;
322  end if;
323  end if;
324 end process;
325 
326 L1A_delay_out <= L1A_delay_2;
327 -- Bunch counter: The Bunch Counter is a local 12-bit counter that increments each LHC clock.
328 -- It counts to a value of 3563 (x"DEB")and then rolls over to 0
329 
330 --process (cttc_user_clk) begin
331 -- if rising_edge (cttc_user_clk) then
332 -- if (reset ='1' or BCR = '1' or BCN = X"DEB") then
333 -- BCN <= X"000";
334 -- elsif seq = "01" then
335 -- BCN <= (BCN + 1);
336 -- else
337 -- BCN <= BCN;
338 -- end if;
339 -- end if;
340 -- end process;
341 
342 
343 --///////////////BCR CRC Check ///////////////
344 --to confirm BCR with ttc_crc_ok, the BCR needs to be delayed by one cycle to pick of the following seq=1.
345 --Then, the BCN_count would need to be set to 001 instead of 000
346 --elsif (BCR_delay = '1')and (seq = "01") and (ttc_crc_ok = '1') then
347 -- BCN_count <= X"001";
348 -- this change has not yet been made because it needs to be specifically tested in the STF to avoid BCN mismatches.
349 
350 ---this is a new attempt at getting BCN to be correct after discussion in April '21 L1Calo-UK meeting
351 process (cttc_user_clk) begin
352  if rising_edge (cttc_user_clk) then
353  if (reset ='1') then
354  BCN_count <= X"000";
355  elsif (BCR_delay = '1')and (seq = "01") and (ttc_crc_ok = '1') then --to revert, change BCR_delay to BCR and BCN_count to x"000"
356  BCN_count <= X"001";
357  elsif (BCN = X"DEB") and (seq = "01") then
358  BCN_count <= X"000";
359  elsif seq = "01" then
360  BCN_count <= (BCN_count + 1);
361  else
362  BCN_count <= BCN_count;
363  end if;
364  end if;
365  end process;
366 
367 BCN <= BCN_count + bcn_adjustment;
368 
372 --upgraded from 24 to 32-bits 25-Nov-2021
373 --process (cttc_user_clk) begin
374 process (cttc_user_clk, reset, event_count_reset) begin
375  if ((reset or event_count_reset) = '1') then
376  Event_Counter <= X"00000000";
377  elsif rising_edge (cttc_user_clk) then
378  if (ECR = '1') then
379 -- Event_Counter <= X"FFF";
380  Event_Counter <= X"FFFFFFFF";
381  elsif (L1A = '1') and (seq = "01") then
382  Event_Counter <= (Event_Counter + 1);
383  else
384  Event_Counter <= Event_Counter;
385  end if;
386  end if;
387 end process;
388 
389 event_count <= Event_Counter;
390 
391 
392 
393 -- Orbit Counter: Local 16-bit counter that increments on each Bunch Counter roll-over (or BCR?)
394 -- Assume for the moment that it resets to 0000
395 
396 process (cttc_user_clk) begin
397  if rising_edge (cttc_user_clk) then
398 -- if ((reset or orbit_count_reset) ='1' or BCR = '1') then
399  if ((reset or orbit_count_reset) ='1') then
400  Orbit <= X"0000";
401  elsif BCN = X"DEB" then
402  Orbit <= (Orbit + 1);
403  end if;
404  end if;
405  end process;
406 
407 --create delayed ECR
408 process (cttc_user_clk) begin
409  if rising_edge (cttc_user_clk) then
410  ECR_delay <= ECR;
411  end if;
412  end process;
413 
414 
415 ----ECRID: 8-bit extended Level-1 ID, obtained by counting TTC L1ID reset commands
416 -- --or should it be Event Counter rollovers?
417 -- --in this version it increments ECRID on an EC rollover, byt not on ECR
418 ----this definition needs to be checked!!!!!
419 --
420 --process (cttc_user_clk) begin
421 -- if rising_edge (cttc_user_clk) then
422 -- if (reset ='1') then
423 -- ECRID <= X"00";
424 -- elsif (EC = X"FFF") and (ECR_delay ='0') then --if ECR_delay is 0, then the overflow is not due to an ECR
425 -- ECRID <= (ECRID + 1);
426 -- end if;
427 -- end if;
428 -- end process;
429 
430 
431 
432 
433 
434 --L1ID error flag: if the local EC doesn't match the TTC L1ID
435 process (cttc_user_clk) begin
436  if rising_edge (cttc_user_clk) then
437  if (reset ='1') or (L1ID_32 = Event_Counter) then
438  L1ID_error <= '0';
439  elsif (L1ID_32 /= Event_Counter) then
440  L1ID_error <= '1';
441  end if;
442  end if;
443  end process;
444 
445 --
446 
447 --ttc_crc_ok <='1'; --temp until crc is implemented
448 ttc_crc_ok <= '1' when ((proposed_crc = crc_gen) and (seq = "01")) else '0';
449 CTTC_CRC_error <= not ttc_crc_ok and not seq(1) and seq(0);
450 
451 
452 --process (cttc_user_clk) begin
453 -- if rising_edge (cttc_user_clk) then
454 -- if seq = "01" then
455 -- header_fifo_wen <= L1A_delay and (ttc_crc_ok or TTC_CRC_ignore);
456 -- else
457 -- header_fifo_wen <= '0';
458 -- end if;
459 -- end if;
460 --end process;
461 
462  --header_fifo_wen <= L1A_delay and not seq(1) and seq(0) and (ttc_crc_ok or TTC_CRC_ignore);
463  header_fifo_wen <= L1A_delay and not seq(1) and seq(0) and event_en and (ttc_crc_ok or TTC_CRC_ignore);
464 
465  --DSET header fifo write enable removes the "event_en" term because there is no ping-pong for DSET packets
466  dset_header_fifo_wen <= L1A_delay and not seq(1) and seq(0) and (ttc_crc_ok or TTC_CRC_ignore);
467 
468 --Header fifo bit definitions
469 --note that Stream ID doesnotpass through this fifo because it originates at the fex (not ttc)
470 --fifo rst to be changed to fifo_reset
471 fifo_reset <= reset or TTC_fifo_rst;
472 
473 ttc_fifo : ttc_header_fifo
474  PORT MAP (
475 -- rst => reset,
476  rst => fifo_reset,
477  wr_clk => cttc_user_clk,
478  rd_clk => pp_clk,
479  din(11 downto 0) => BCN,
480  din(35 downto 12) => L1ID,
481  din(43 downto 36) => ECRID,
482  din(59 downto 44) => orbit,
483  din(63 downto 60) => x"0",
484  wr_en => header_fifo_wen,
485  rd_en => header_read_en,
486  dout => master_header_i,
487  full => header_fifo_full_i,
488  almost_full => open,
489  empty => header_fifo_empty_i,
490  valid => ttc_fifo_valid,
491  underflow => open,
492  rd_data_count => header_fifo_level_i
493  );
494 
495 header_fifo_valid <= ttc_fifo_valid and not header_fifo_empty_i;
496 header_fifo_empty <= header_fifo_empty_i;
497 
498 --The bulk_ttc_fifo is really for DSET packet header information (not bulk)
499 --fifo rst to be changed to fifo_reset during testing (enables register to clear the fifo)
500 bulk_ttc_fifo : ttc_header_fifo
501  PORT MAP (
502 -- rst => reset,
503  rst => fifo_reset,
504  wr_clk => cttc_user_clk,
505  rd_clk => pp_clk,
506  din(11 downto 0) => BCN,
507  din(35 downto 12) => L1ID,
508  din(43 downto 36) => ECRID,
509  din(59 downto 44) => orbit,
510  din(63 downto 60) => x"0",
511  wr_en => DSET_header_fifo_wen,
512  rd_en => bulk_header_read_en,
513  dout => bulk_master_header_i,
514  full => bulk_header_fifo_full_i,
515  empty => bulk_header_fifo_empty_i,
516  valid => bulk_ttc_fifo_valid,
517  underflow => bulk_header_fifo_underflow,
518  rd_data_count => bulk_fifo_count
519  );
520 
521 bulk_header_fifo_valid <= bulk_ttc_fifo_valid and not bulk_header_fifo_empty_i;
522 bulk_header_fifo_empty <= bulk_header_fifo_empty_i;
523 bulk_header_fifo_full <= bulk_header_fifo_full_i;
524 bulk_master_header <= bulk_master_header_i;
525 
526 
527 ila_bulk_ttc_fifo: ila_bulk_ttc
528 port map (
529 clk => pp_clk,
530 probe0 => seq, --2
531 probe1(0) => L1A, --1
532 probe2(0) => DSET_header_fifo_wen, --1
533 probe3(0) => bulk_header_read_en, --1
534 probe4(0) => L1A_delay,
535 probe5(0) => event_en,
536 probe6(0) => ttc_crc_ok,
537 probe7(0) => TTC_CRC_ignore,
538 probe8(0) => bulk_header_fifo_full, --1
539 probe9(0) => bulk_header_fifo_empty_i, --1
540 probe10(0) => bulk_header_fifo_underflow, --1
541 probe11(0) => bulk_ttc_fifo_valid, --1
542 probe12 => bulk_fifo_count, --9
543 probe13 => bulk_master_header_i(35 downto 12) --24
544 
545 );
546 
547 --TTC register
548 process (cttc_user_clk) begin
549  if rising_edge (cttc_user_clk) then
550  if header_fifo_wen = '1' then
551  ttc_reg_i(11 downto 0) <= BCN;
552  ttc_reg_i(35 downto 12) <= L1ID;
553  ttc_reg_i(43 downto 36) <= ECRID;
554 -- ttc_reg_i(59 downto 44) <= orbit;
555  end if;
556  end if;
557 end process;
558 
559 ttc_reg <= ttc_reg_i;
560 orbit_count <= orbit;
561 
562 --instance the crc circuit - crc is calculated based upon 32-bi inputs
563 cttc_crc : osum_crc9d32
564  Port Map (
565  clock => cttc_user_clk,
566  crc_start => crc_start,
567  d_in => cttc_word, --- : in std_logic_vector(31 downto 0);
568  crc_out => crc_gen
569  ); --: out std_logic_vector(8 downto 0));
570 
571 
572  crc_word_0 <= ttc_word_0(31 downto 8) & "00000000";
573  crc_word_3 <= "000000000" & ttc_word_3(22 downto 0);
574 --muxing all 4 of the combined_TTC words into the CRC generator as they arive
575  with seq select
576  cttc_word <= crc_word_0 when "01",
577  ttc_word_1 when "10",
578  ttc_word_2 when "11",
579  -- ttc_word_3(22 downto 0) & "000000000" when "00",
580  -- ("000000000" & ttc_word_3(22 downto 0)) when "00",
581  crc_word_3 when "00",
582  (others => '-') when others;
583  --crc_start <= not seq(0) or seq(1);
584  crc_start <= (not seq(1)) and seq(0);
585 
586 master_header <= master_header_i;
587 header_fifo_level <= header_fifo_level_i;
588 header_fifo_full <= header_fifo_full_i;
589 
590 
592 
602 process (event_sel(1), event_sel(0), rod_slot, L1ID(0))
603 variable sel_bus : std_logic_vector(2 downto 0);
604  begin
605  sel_bus := event_sel(1) & event_sel(0) & rod_slot;
606  case sel_bus is
607  when "000" =>
608  event_en <= not (L1ID(0));
609  when "001" =>
610  event_en <= (L1ID(0));
611  when "010" =>
612  event_en <= L1ID(0);
613  when "011" =>
614  event_en <= not L1ID(0);
615  when "100" | "101" =>
616  event_en <= '0';
617  when others =>
618  event_en <= '1';
619  end case;
620 end process;
621 
622 
623 
624 
625 ila_ttc_fifo_in: ila_ttc_in port map (
626 clk => cttc_user_clk,
627 probe0 => seq, --2
628 probe1(0) => L1A, --1
629 probe2(0) => header_fifo_wen, --1
630 probe3 => L1id, --24
631 probe4 => BCN, --12
632 probe5 => ECRID, --8
633 probe6 => orbit, --16
634 
635 
636 probe7 => ttc_word_0,
637 probe8 => ttc_word_1,
638 probe9 => ttc_word_2,
639 probe10 => ttc_word_3,
640 
641 probe11 => cttc_word,
642 probe12(0) => crc_start,
643 probe13 => crc_gen,
644 probe14 => proposed_crc,
645 probe15(0) => ttc_crc_ok,
646 probe16(0) => CTTC_CRC_error
647 
648 );
649 
650 ila_ttc_fifo_out: ila_ttc_out port map (
651 clk => pp_clk,
652 probe0 => seq, --2
653 probe1(0) => L1A, --1
654 probe2(0) => header_read_en, --1
655 probe3(0) => header_fifo_full_i,
656 probe4 =>header_fifo_level_i, --9
657 probe5(0) =>ttc_fifo_valid,
658 probe6 =>master_header_i, --64
659 probe7(0) =>l1id_mis_stretch
660 );
661 
662 
663 
664 l1id_continuity_checker : l1id_cont_check
665  Port Map (
666 
667  clock => cttc_user_clk,
668  reset => reset,
669  -- clr_errors : in STD_LOGIC;
670  L1A => L1A,
671  ECR => ECR,
672  L1id => L1ID,
673  ECRid => ECRID,
674  timeout_threshold => timeout_threshold,
675  l1id_continuity_control => l1id_continuity_control,
676  l1id_continuity_status => l1id_continuity_status,
677  l1id_local_miss => l1id_local_miss,
678  l1id_ttc_miss => l1id_ttc_miss,
679 
680  l1id_error_count => l1id_error_count,
681  repeat_counter => repeat_counter
682 
683  );
684 
685 
686 --synchronise the felix backpressure signals to the packet processor clock
687 process (pp_clk) begin
688  if (rising_edge(pp_clk)) then
689  flx_bp_sync_0 <= ttc_word_0(31 downto 20);
690  flx_bp_sync_1 <= flx_bp_sync_0;
691  end if;
692 end process;
693 
694 flx_backpressure <= flx_bp_sync_1;
695 
696 
697 end RTL;
l1id_cont_check
Definition: l1id_cont_check.vhd:35
osum_crc9d32
Definition: osum_crc9d32.vhd:28
ttc_info.RTL
Definition: ttc_info.vhd:109
ila_ttc_fifo_in
ila_ttc_in ila_ttc_fifo_inila_ttc_fifo_in
Definition: ttc_info.vhd:648
ttc_info
Definition: ttc_info.vhd:51
Generated on Sat Dec 14 2024 13:33:14 for ROD firmware by   doxygen 1.9.1