dummy_chan_in.vhd

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-- when only one event processor is used, this block must be added to create a dummy chan_in to the event processor
-- when the event processors current_chan reaches 2, the chan_out can be incremented to 1
-- then it must stay behind the event processor's current chan in a circular fashion
--
-- Company: 
-- Engineer: 
-- 
-- Create Date: 25.08.2017 16:43:48
-- Design Name: 
-- Module Name: dummy_chan_in - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity dummy_chan_in is
    Port ( current_chan : in STD_LOGIC_VECTOR (4 downto 0);
           chan_out     : out STD_LOGIC_VECTOR (4 downto 0);
           num_chan     : in STD_LOGIC_VECTOR (4 downto 0); 
           clock        : in STD_LOGIC;
           reset        : in STD_LOGIC);
end dummy_chan_in;
 
architecture RTL of dummy_chan_in is
signal first_event   : std_logic;
signal chan_out_i    : STD_LOGIC_VECTOR (4 downto 0);
 
 
begin
process (clock) begin
           if rising_edge (clock) then
               if (reset = '1')  then
                  first_event <= '1';
                  chan_out_i <= "00000";
               elsif (first_event = '1') and (current_chan = x"00010")  then 
                  first_event <= '0';
                  chan_out_i <= "00001";
               elsif (first_event ='0') then 
                  if (current_chan >= "00001") then 
                    chan_out_i <= (current_chan - 1); 
                  else 
                     chan_out_i <= num_chan; 
                  end if; 
               end if; 
            end if; 
 end process; 
 
 chan_out <= chan_out_i;
 
 end RTL;