priority_encoder.vhd

----------------------------------------------------------------------------------
-- Company: University of Cambridge 
-- Engineer: Ed Flaherty
-- 
-- Create Date: 20.08.2019 11:26:23
-- Design Name: 
-- Module Name: priority_encoder - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity priority_encoder is
    Port ( 
           chan_ena : in STD_LOGIC_VECTOR (23 downto 0);
           clock : in STD_LOGIC;
           first_chan : out STD_LOGIC_vector(4 downto 0);
           last_chan : out STD_LOGIC_vector(4 downto 0)
           );
end priority_encoder;
 
architecture RTL of priority_encoder is
 
begin
 
---------------------------------------------------------------------
--------   calculate the lowest channel that is running---------
--------------------------------------------------------------------- 
--high_low : PROCESS(chan_ena)
high_low : PROCESS(clock)
   VARIABLE low_chan : integer := 0;
begin
  if rising_edge(clock) then
   for i in 23 downto 0 loop
      if chan_ena(i) = '1' then 
         low_chan := i;
      end if;      
   end loop;
 end if;  
first_chan <= std_logic_vector(to_unsigned(low_chan,5));
end process;
 
---------------------------------------------------------------------
-------- calculate the highest channel that is running---------
--------------------------------------------------------------------- 
--low_high : PROCESS(chan_ena)
low_high : PROCESS(clock)
   VARIABLE high_chan : integer := 23;
begin
  if rising_edge(clock) then
   for i in 0 to 23 loop
      if chan_ena(i) = '1' then 
         high_chan := i;
      end if;
   end loop;
  end if; 
last_chan <= std_logic_vector(to_unsigned(high_chan,5));
end process;
 
end RTL;