Index of /efex/firmware/ROD/official/v0.5.25/rod_efex-v0.5.25/reports
Name Last modified Size Description
Parent Directory -
clk_wiz_240_synth_1.log 2023-10-05 11:22 21K
packet_processor_clock_synth_1.log 2023-10-05 11:22 22K
aurora_in_fifo_synth_1.log 2023-10-05 11:22 51K
top_rod_efex_utilization_synth.rpt 2023-10-05 11:22 11K
processor_in_fifo_synth_1.log 2023-10-05 11:22 47K
DPram_32b_utilization_synth.rpt 2023-10-05 11:22 7.6K
vio_fullmode_reset_synth_1.log 2023-10-05 11:22 33K
rod_ROctrl_mux_ila_synth_1.log 2023-10-05 11:22 223K
error_ila_synth_1.log 2023-10-05 11:22 228K
vio_top_utilization_synth.rpt 2023-10-05 11:22 7.8K
aurora_rx_1q_utilization_synth.rpt 2023-10-05 11:22 8.3K
data_fifo_vio_synth_1.log 2023-10-05 11:22 563
error_ila_utilization_synth.rpt 2023-10-05 11:22 8.4K
impl_1.log 2023-10-05 11:22 274K
rod_ROctrl_mux_ila_utilization_synth.rpt 2023-10-05 11:22 8.4K
ila_ttc_in_utilization_synth.rpt 2023-10-05 11:22 8.4K
backplane_control_ila_synth_1.log 2023-10-05 11:22 218K
clk_wiz_240_utilization_synth.rpt 2023-10-05 11:22 7.6K
bulk_data_fifo_utilization_synth.rpt 2023-10-05 11:22 8.0K
processor_in_fifo_utilization_synth.rpt 2023-10-05 11:22 8.3K
ila_ev_builder_synth_1.log 2023-10-05 11:22 246K
ila_mgtfsm_synth_1.log 2023-10-05 11:22 223K
fifo1KB_34bit_synth_1.log 2023-10-05 11:22 49K
ethernet_mac_rgmii_synth_1.log 2023-10-05 11:22 88K
ila_ttc_in_synth_1.log 2023-10-05 11:22 232K
pp_ctrl_vio_synth_1.log 2023-10-05 11:22 33K
event_builder_fifo_synth_1.log 2023-10-05 11:22 583
axis_dwidth_64_32_utilization_synth.rpt 2023-10-05 11:22 7.8K
vio_ip_address_synth_1.log 2023-10-05 11:22 32K
aurora_rx_4l_64b_synth_1.log 2023-10-05 11:22 135K
aurora_fifo_out_ila_utilization_synth.rpt 2023-10-05 11:22 8.4K
fm_status_fifo_utilization_synth.rpt 2023-10-05 11:22 8.2K
aurora_fifo_out_ila_synth_1.log 2023-10-05 11:22 225K
ila_ttc_out_utilization_synth.rpt 2023-10-05 11:22 8.5K
ila_fifo_utilization_synth.rpt 2023-10-05 11:22 8.4K
ttc_header_fifo_synth_1.log 2023-10-05 11:22 51K
axis_input_fifo_utilization_synth.rpt 2023-10-05 11:22 8.0K
bulk_data_fifo_synth_1.log 2023-10-05 11:22 41K
ila_bulk_ttc_utilization_synth.rpt 2023-10-05 11:22 8.5K
DPram_32b_synth_1.log 2023-10-05 11:22 35K
chan_map_ila_utilization_synth.rpt 2023-10-05 11:22 8.4K
aurora_fifo_in_ila_synth_1.log 2023-10-05 11:22 228K
rgmii_rx_fifo_2_synth_1.log 2023-10-05 11:22 41K
top_rod_efex_utilization_placed.rpt 2023-10-05 11:22 15K
backplane_control_ila_utilization_synth.rpt 2023-10-05 11:22 8.4K
MGT_combined_ttc_rx_synth_1.log 2023-10-05 11:22 62K
ila_1_synth_1.log 2023-10-05 11:22 216K
bulk_ila_utilization_synth.rpt 2023-10-05 11:22 8.4K
ila_2_synth_1.log 2023-10-05 11:22 231K
ila_mgtfsm_utilization_synth.rpt 2023-10-05 11:22 8.4K
rod_RO_Tx_synth_1.log 2023-10-05 11:22 51K
chan_crc_ila_synth_1.log 2023-10-05 11:22 226K
vio_fullmode_reset_utilization_synth.rpt 2023-10-05 11:22 7.9K
vio_top_synth_1.log 2023-10-05 11:22 32K
chan_crc_ila_utilization_synth.rpt 2023-10-05 11:22 8.5K
ila_ttc_out_synth_1.log 2023-10-05 11:22 223K
ila_fifo_synth_1.log 2023-10-05 11:22 228K
vio_0_synth_1.log 2023-10-05 11:22 686
top_rod_efex_control_sets_placed.rpt 2023-10-05 11:22 3.7M
axis_data_fifo_0_utilization_synth.rpt 2023-10-05 11:22 8.2K
fm_status_fifo_synth_1.log 2023-10-05 11:22 50K
ila_l1id_cont_utilization_synth.rpt 2023-10-05 11:22 8.4K
vio_ip_address_utilization_synth.rpt 2023-10-05 11:22 7.8K
ila_1_utilization_synth.rpt 2023-10-05 11:22 8.3K
axis_data_fifo_0_synth_1.log 2023-10-05 11:22 46K
ila_fullmode_synth_1.log 2023-10-05 11:21 229K
axi_ila_1_utilization_synth.rpt 2023-10-05 11:21 8.5K
aurora_fifo_in_ila_utilization_synth.rpt 2023-10-05 11:21 8.5K
axi_ila_1_synth_1.log 2023-10-05 11:21 229K
packet_processor_clock_utilization_synth.rpt 2023-10-05 11:21 7.7K
aurora_rx_4l_64b_utilization_synth.rpt 2023-10-05 11:21 8.4K
synth_1.log 2023-10-05 11:21 941K
chan_map_ila_synth_1.log 2023-10-05 11:21 218K
vio_ttc_utilization_synth.rpt 2023-10-05 11:21 7.8K
MGT_combined_ttc_rx_utilization_synth.rpt 2023-10-05 11:21 8.4K
ila_ev_builder_utilization_synth.rpt 2023-10-05 11:21 8.5K
axis_dwidth_64_32_synth_1.log 2023-10-05 11:21 32K
top_rod_efex_io_placed.rpt 2023-10-05 11:21 604K
ila_l1id_cont_synth_1.log 2023-10-05 11:21 230K
pp_ctrl_vio_utilization_synth.rpt 2023-10-05 11:21 7.8K
aurora_rx_1q_synth_1.log 2023-10-05 11:21 130K
rgmii_rx_fifo_2_utilization_synth.rpt 2023-10-05 11:21 8.0K
ethernet_mac_rgmii_utilization_synth.rpt 2023-10-05 11:21 9.1K
rod_RO_Tx_utilization_synth.rpt 2023-10-05 11:21 8.3K
top_rod_efex_drc_opted.rpt 2023-10-05 11:21 8.1K
aurora_in_fifo_utilization_synth.rpt 2023-10-05 11:21 8.3K
axis_input_fifo_synth_1.log 2023-10-05 11:21 48K
axi_ch0_synth_1.log 2023-10-05 11:21 221K
debug_ila_ed1_synth_1.log 2023-10-05 11:21 235K
ila_bulk_ttc_synth_1.log 2023-10-05 11:21 230K
vio_ttc_synth_1.log 2023-10-05 11:21 32K
ttc_header_fifo_utilization_synth.rpt 2023-10-05 11:21 8.2K
bulk_ila_synth_1.log 2023-10-05 11:21 224K
ila_fullmode_utilization_synth.rpt 2023-10-05 11:21 8.5K
debug_ila_ed1_utilization_synth.rpt 2023-10-05 11:21 8.5K
hierarchical_utilization.txt 2023-10-05 11:21 3.7M
axi_ch0_utilization_synth.rpt 2023-10-05 11:21 8.3K
ila_2_utilization_synth.rpt 2023-10-05 11:21 8.4K
fifo1KB_34bit_utilization_synth.rpt 2023-10-05 11:21 8.2K