eFEX Firmware

This is the firmware eFEX board FPGAs.

This project uses Hog.

Documentation

The eFEX firmware documentation here is created using Doxygen. It is intended for specialists who are required to work on, or with, the firmware (e.g. to maintain it). For a broader overview of the eFEX, including the hardware, see the eFEX Technical Specification.

That document also contains links to others, such as those that specify the data formats on the real-time and readout paths.

The eFEX module houses 5 FPGAs:

1 Control FPGA
4 Processor FPGAs

The 4 Processor FPGAs have differing pin-outs and functionalities, but the firmware for all 4 FPGAs is built from the same set of source files; generic parameters are used to tailor the build for each FPGA. The functionality implemented by the Processor FPGAs can be split into real-time and readout paths (plus slow control). On the real-time path, all of the Processor FPGAs perform the following tasks:

receive calorimeter data at 11.2 GB/s;
align these data in time;
run feature-extraction algorithms on the data and form Trigger Objects (TOBs) for electro-magnetic (EM) and Tau objects;
sort these TOBs.

Additionally, 2 of the Processor FPGAs receive TOBs from the others and sort them over the whole eFEX module: Processor FPGA [which?] sorts the EM TOBS, and Processor FPGA [which?] sorts the Tau TOBS. Those 2 FPGAs then transmit the sorted TOBs to L1Topo at 11.2 Gb/s.

On the readout path, each Processor FPGA records the TOB data in scrolling memories, and on receipt of an L1A, transmits these to the Control FPGA. The input calorimeter data are also recorded and transmitted in the event of an input error, or other programmable condition.

The Control FPGA implements the final stage of the eFEX readout path, plus the eFEX interfaces to the TTC and slow-control (IPBus) networks. On the readout path, it receives data streams from the 4 Processor FPGAs and merges them, before transmission downstream to the L1Calo ROD module at 6.4 Gb/s. On the TTC network, the Control FPGA receives the signals, decodes them and transmits a subset to the Processor FPGAs. For slow control, the Control FPGA implements the main control interface of the module, and also distributes signals to the Processor FPGAs, which implement subsidiary interfaces. In addition to the main ('user') firmware loads described about, the Control and Processor FPGAs all have Golden images.

These are versions of the firmware that implement the same control interfaces as above, but which lack most of the internal functionality. They are the loads to which an eFEX FPGA reverts if there is an error when configuring that FPGA with the user load. They provide sufficient interfaces to that FPGA and its configuration FLASH RAM to allow that FPGA to be restored to a working firmware load. The Golden images are built from the same suite of source files as the User images, using generic parameters to customise the builds.

Repository instructions:

After cloning the repository (with –recursive), just run:

./CreateProject.sh efex_processor.1

or

./CreateProject.sh efex_control

Launch the command with no argument to get a list of all the projects in the repository.

All projects will be created in the Projects directory.