top_efex_processor Entity Reference

Top of the process FPGA. More...

Inheritance diagram for top_efex_processor:

Entities
Behavioral	architecture
	Top of the process FPGA. More...

Libraries
IEEE
unisim
algolib
ipbus_lib
infrastructure_lib
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
numeric_std
VComponents
AlgoDataTypes	Package <AlgoDataTypes>
ipbus
all
ipbus_decode_L1CaloEfexProcessor	Package <ipbus_decode_L1CaloEfexProcessor>
synch_type	Package <synch_type>
EfexDataFormats	Package <EfexDataFormats>
mgt_type	Package <mgt_type>
ProcessorFPGAPackage	Package <ProcessorFPGAPackage>
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>
tob_rdout_comp_pkg
golden	Package <golden>

Generics
FLAVOUR	integer := 0
	Integer used to distinguish different FPGAs having a slightly different firmware.
GLOBAL_DATE	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Date format DDMMYYYY in decimal.
GLOBAL_TIME	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Time format 00HHMMSS in decimal.
GLOBAL_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the repository.
GLOBAL_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the repository (format: MMmmpppp in hex)
TOP_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the tcl file.
TOP_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the top folder, see TOP_SHA.
CON_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the tcl file.
CON_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the top folder, see TOP_SHA.
XML_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the XMLs.
XML_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the XMLs.
HOG_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the Hog submodule.
HOG_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of Hog.
ALGOLIB_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git sha.
ALGOLIB_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of algolib library (format: MMmmpppp in hex)
INFRASTRUCTURE_LIB_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA.
INFRASTRUCTURE_LIB_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of infrastructure library (format: MMmmpppp in hex)
TOB_RDOUT_LIB_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA.
TOB_RDOUT_LIB_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the readout library (format: MMmmpppp in hex)
IPBUS_LIB_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the ipbus submodule.
IPBUS_LIB_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the readout library (format: MMmmpppp in hex)
READOUT_ENABLED	boolean := true
INPUT_RAM_ENABLED	boolean := false
OUTPUT_RAMS_ENABLED	boolean := false
SORT_IN_RAM_ENABLED	boolean := false
SORT_OUT_RAM_ENABLED	boolean := false
MGT_ENABLED	boolean := true
MERGE_ENABLED	boolean := true
DATA_PATH_ENABLED	boolean := true
TAU_ALGO_VERSION	std_logic_vector ( 1 downto 0 ) := " 10 "
EG_ALGO_VERSION	std_logic_vector ( 1 downto 0 ) := " 01 "
ENCODING_MODE	integer := 2
	Possible values: -2: Steve's multilinear, -1, Standard multilinear, 0-5 linear encoding shifted by the specifide number of bits.
EFEX_POSITION	integer := 0
	Possible values: 0 dynamic mapping, 1-3 static mapping.
n_channels	natural := 64

Ports
gt_clk125_p	in	std_logic
		125MHz ipbus clock
gt_clk125_n	in	std_logic
		125MHz ipbus clock
master_rx_data	in	std_logic_vector ( 9 downto 0 )
		ipbus interconnections signals
master_tx_pause	in	std_logic
		ipbus interconnections signals
master_tx_data	out	std_logic_vector ( 9 downto 0 )
		ipbus interconnections signals
flash_csn	out	std_logic
flash_mosi	out	std_logic
flash_miso	in	std_logic
flash_led	out	std_logic
ttc_clk_p	in	std_logic
ttc_clk_n	in	std_logic
reset_clk125	in	std_logic
		Reset signal for IPBus clock 125 from Control FPGA.
hardware_addr	in	std_logic_vector ( 11 downto 0 )
fpga_geo_addr	in	std_logic_vector ( 1 downto 0 )
		geographical address of the fpga
VAUXP	in	std_logic
VAUXN	in	std_logic
Vp	in	std_logic
Vn	in	std_logic
efex_in	in	efex_processor_input
efex_out	out	efex_processor_output

Detailed Description

Top of the process FPGA.

This is the top level of the eFEX Processor firmware. The logic implemented here can be grouped into the areas of real-time, readout, control and infrastructure.

Real-Time Logic

This logic implements the core functionality of the eFEX. It forms part of the real-time L1 processing chain that forms the trigger decision. There are 4 Processor FPGAs on the eFEX, and not all of them implement the same real-time logic, as explained below.

Every Processor FPGA performs the following real-time functions:

• Receives 64 channels of serial data at 11.2 Gb/s.
• Transfers these data to the 40.08 MHz LHC clock domain, in the process aligning them to each other and the LHC clock, with a fixed latency.
• Transfers the aligned data to a 200 MHz clock domain and runs electro-magnetic (EM) and Tau feature-extraction algorithms, generating Trigger Objects (TOBs).
• Sorts the EM and Tau TOBs over the FPGA, in order of priority, in the process transfering them to the 280 MHz clock domain. Additionally, 1 Processor FPGAs on every eFEX also performs the following real-time functions.
• Receives EM TOBs from the other 3 Processor FPGAs and sorts them plus its own EM TOBs in order of priority.
• Transmits the 6 highest-priority EM TOBs per BC to Topo, at 11.2 Gb/s. And 1 Processor FPGAs on every eFEX also performs the following real-time functions.
• Receives Tau TOBs from the other 3 Processor FPGAs and sorts them plus its own Tau TOBs in order of priority.
• Transmits the 6 highest-priority Tau TOBs per BC to Topo, at 11.2 Gb/s. Those Processor FPGAs that do not perform this second stage of EM or Tau TOB sorting, transmit their TOBs (either EM or Tau or both) to those FPGAs that do. For each type, up to 6 TOBs are transmitted at 280 Mhz per BC. The real-time logic comprises the following blocks.
• data_path_block (top level of a block that includes data alignment, feature-extraction algorithms and FPGA-level TOB merging)
• IPBusTopMergingModule (module-level TOB merging, plus control interface to that logic. Not implemented in all versions of the Processor FPGA firmware; determined by the generic parameter FLAVOUR.)
• efex_topo_tx (formatting of TOB data for transmission to L1Topo) Readout Logic The readout logic of the Processor FPGA performs the following functions.
• For each BC, the input data, TOBs, and intermediate TOB data (xTOBs) are copied from the real-time logic and held in pipeline memories until the arrival (or not) of the L1A/L0A signal for that BC.
• If an L1A/L0A is received for a BC, some subset of the above data are transmitted downstream on the readout path to the Control FPGA, at 11.2 Gb/s. The subset transmitted depends on the slow-control settings and the current state of the buffer occupancy on the readout path. See the lower levels of the firmware and [ref to data format doc] for details. All of the readout logic is contained with the following block.
• Readout_logic_top (top level of all readout logic)

Control Interface

The control interface is implemented using IP from the IPBus project, which provides access to registers and RAM space within the firmware. For documentation on IPBus, see https://ipbus.web.cern.ch/introduction/ The control interface comprises the following modules.

• proc_FPGAs (IPBus, UDP slave interface to the Control FPGA)
• ipbus_fabric_sel (address-select logic plus data multiplexers)
• common_id_registers (ID registers)
• lib_registers (registers)
• slaves (IPBus-SPI interface to external components)
• startup (Xilinx IP that provides a user interface FPGA configuration and control signals)
• self_configure (FPGA re-configuration control)
• mgt_slaves (control interface of all MGTs)

Infrastructure

The following blocks implement resources that are used by many or all of the other areas of logic.

• clk_resources (clock resources)
• MGT_4_quad_gen (implements all MGTs in the design)

Example of timing diagram

         ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
 CLK:  ──┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─
         ┌───┐ ┌───┐ ┌─┐ ┌─────┐   ┌─┐ ┌─┐
 SIG1: ──┘   └─┘   └─┘ └─┘     └───┘ └─┘ └
         ┌─────┐   ┌─┐   ┌─┐   ┌───┐
 SIG2: ──┘     └───┘ └───┘ └───┘   └────
       ┬─────┬────┬────┬────┬────┬
 Data: │     │ A1 │ A2 │ X  │    │
       ┴─────┴────┴────┴────┴────┴

Author

Mohammed Syiad

Francesco Gonnella

Saeed Taghavi

Definition at line 96 of file top_efex_processor.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd