eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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ProcessorFPGAPackage Package Reference
Package Body >> ProcessorFPGAPackage

Functions

std_logic_vector   F_MGT_QUAD_ENABLE ( fpga_number: in in integer )
integer   F_MGT_USE_OTHER_CLK_N ( fpga_number: in in integer )
std_logic_vector   F_IPBUS_PORT_N ( fpga_number: in in integer )
std_logic_vector   F_MGT_USE_OTHER_CLK ( fpga_number: in in integer )
std_logic_vector   F_MGT_TX_POWER ( fpga_number: in in integer )
std_logic_vector   F_MGT_RX_POWER ( fpga_number: in in integer )
std_logic   F_ENABLE_MERGING ( fpga_number: in in integer )
bit_vector   xadc_reg48 ( fpga_number: in in integer )
bit_vector   xadc_reg49 ( fpga_number: in in integer )

Procedures

  MGT_SELECTOR_RX(
signal fpga_number: in integer
signal in_BC_Reg_sel: in std_logic_vector ( 319 downto 0 )
signal in_mux_sel: in std_logic_vector ( 319 downto 0 )
signal in_delay_num: out std_logic_vector ( 319 downto 0 )
signal in_bc_cntr_0: out std_logic_vector ( 139 downto 0 )
signal in_bc_cntr_1: out std_logic_vector ( 139 downto 0 )
signal in_bc_cntr_2: out std_logic_vector ( 139 downto 0 )
signal in_bc_cntr_3: out std_logic_vector ( 139 downto 0 )
signal in_bc_mux_cntr_0: out std_logic_vector ( 139 downto 0 )
signal in_bc_mux_cntr_1: out std_logic_vector ( 139 downto 0 )
signal in_bc_mux_cntr_2: out std_logic_vector ( 139 downto 0 )
signal in_bc_mux_cntr_3: out std_logic_vector ( 139 downto 0 )
signal in_mgt_RXUSRCLK_OUT: in std_logic_vector ( 79 downto 0 )
signal in_enable_mgt: in std_logic_vector ( 79 downto 0 )
signal in_bcn_synch: out std_logic_vector ( 79 downto 0 )
signal in_crc_error_chan: out std_logic_vector ( 79 downto 0 )
signal in_notable_error: in std_logic_vector ( 79 downto 0 )
signal in_disperr_error: in std_logic_vector ( 79 downto 0 )
signal in_rx_resetdone: in std_logic_vector ( 79 downto 0 )
signal out_BC_Reg_sel: out std_logic_vector ( 255 downto 0 )
signal out_mux_sel: out std_logic_vector ( 255 downto 0 )
signal out_delay_num: in std_logic_vector ( 255 downto 0 )
signal out_bc_cntr_0: in std_logic_vector ( 111 downto 0 )
signal out_bc_cntr_1: in std_logic_vector ( 111 downto 0 )
signal out_bc_cntr_2: in std_logic_vector ( 111 downto 0 )
signal out_bc_cntr_3: in std_logic_vector ( 111 downto 0 )
signal out_bc_mux_cntr_0: in std_logic_vector ( 111 downto 0 )
signal out_bc_mux_cntr_1: in std_logic_vector ( 111 downto 0 )
signal out_bc_mux_cntr_2: in std_logic_vector ( 111 downto 0 )
signal out_bc_mux_cntr_3: in std_logic_vector ( 111 downto 0 )
signal out_mgt_RXUSRCLK_OUT: out std_logic_vector ( 63 downto 0 )
signal out_enable_mgt: out std_logic_vector ( 63 downto 0 )
signal out_bcn_synch: in std_logic_vector ( 63 downto 0 )
signal out_crc_error_chan: in std_logic_vector ( 63 downto 0 )
signal out_disperr_error: out std_logic_vector ( 63 downto 0 )
signal out_notable_error: out std_logic_vector ( 63 downto 0 )
signal out_rx_resetdone: out std_logic_vector ( 63 downto 0 )
signal in_MGT_Commadet: in std_logic_vector ( 79 downto 0 )
signal in_MGT_Data: in mgt_rxdata_array ( 19 downto 0 )
signal out_MGT_Commadet: out std_logic_vector ( 63 downto 0 )
signal out_MGT_Data: out mgt_rxdata_array ( 15 downto 0 )
signal in_rxdata_mgt0: out std_logic_vector ( 639 downto 0 )
signal in_rxdata_mgt1: out std_logic_vector ( 639 downto 0 )
signal in_rxdata_mgt2: out std_logic_vector ( 639 downto 0 )
signal in_rxdata_mgt3: out std_logic_vector ( 639 downto 0 )
signal out_rxdata_mgt0: in std_logic_vector ( 511 downto 0 )
signal out_rxdata_mgt1: in std_logic_vector ( 511 downto 0 )
signal out_rxdata_mgt2: in std_logic_vector ( 511 downto 0 )
signal out_rxdata_mgt3: in std_logic_vector ( 511 downto 0 )
signal in_ram_data_mgt0: in std_logic_vector ( 4559 downto 0 )
signal in_ram_data_mgt1: in std_logic_vector ( 4559 downto 0 )
signal in_ram_data_mgt2: in std_logic_vector ( 4559 downto 0 )
signal in_ram_data_mgt3: in std_logic_vector ( 4559 downto 0 )
signal out_ram_data_mgt0: out std_logic_vector ( 3647 downto 0 )
signal out_ram_data_mgt1: out std_logic_vector ( 3647 downto 0 )
signal out_ram_data_mgt2: out std_logic_vector ( 3647 downto 0 )
signal out_ram_data_mgt3: out std_logic_vector ( 3647 downto 0 )
signal in_align_frame: in std_logic_vector ( 79 downto 0 )
signal out_align_frame: out std_logic_vector ( 63 downto 0 )
signal in_kchar: in std_logic_vector ( 79 downto 0 )
signal out_kchar: out std_logic_vector ( 63 downto 0 )
)
  MGT_SELECTOR_TX(
signal fpga_number: in integer
signal in_mgt_usr_clk: in std_logic_vector ( 79 downto 0 )
signal in_txdata_0: in std_logic_vector ( 33 downto 0 )
signal in_txdata_1: in std_logic_vector ( 33 downto 0 )
signal in_txdata_2: in std_logic_vector ( 33 downto 0 )
signal in_txdata_3: in std_logic_vector ( 33 downto 0 )
signal in_txdata_4: in std_logic_vector ( 33 downto 0 )
signal in_txdata_5: in std_logic_vector ( 33 downto 0 )
signal in_txdata_6: in std_logic_vector ( 33 downto 0 )
signal in_txdata_7: in std_logic_vector ( 33 downto 0 )
signal in_txdata_8: in std_logic_vector ( 33 downto 0 )
signal in_txdata_9: in std_logic_vector ( 33 downto 0 )
signal in_txdata_10: in std_logic_vector ( 33 downto 0 )
signal in_txdata_11: in std_logic_vector ( 33 downto 0 )
signal in_topo_k: in std_logic
signal in_raw_k: in std_logic
signal in_topo_data: in std_logic_vector ( 31 downto 0 )
signal in_raw_data: in std_logic_vector ( 31 downto 0 )
signal out_topo_tob_clk: out std_logic
signal out_topo_raw_clk: out std_logic
signal out_mgt_usr_clk: out std_logic_vector ( 11 downto 0 )
signal out_txcharisk_quad_array: out mgt_txcharisk_array ( 19 downto 0 )
signal out_txdata_quad_array: out mgt_txdata_array ( 19 downto 0 )
)

Libraries

IEEE 
infrastructure_lib 

Use Clauses

STD_LOGIC_1164 
NUMERIC_STD 
mgt_type  Package <mgt_type>

Constants

eFEX_mapping  eFEX_mapping_array := ( x " C " , x " B " , x " 0 " , x " A " , x " 1 " , x " 9 " , x " 2 " , x " 8 " , x " 3 " , x " 7 " , x " 4 " , x " 6 " , x " 5 " , x " C " , x " C " , x " C " )

Types

ecrid_reg_array  ( 3 downto 0 ) std_logic_vector ( 7 downto 0 )
eFEX_mapping_array  ( 15 downto 0 ) std_logic_vector ( 3 downto 0 )

Detailed Description

Definition at line 8 of file ProcessorFPGAPackage.vhd.

The documentation for this class was generated from the following file:
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