eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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ProcessorFPGAPackage.vhd
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.all;
3 use IEEE.NUMERIC_STD.all;
4 
5 library infrastructure_lib;
6 use infrastructure_lib.mgt_type.all;
7 
8 package ProcessorFPGAPackage is
9  -- Common between control and processors
10  type ecrid_reg_array is array(3 downto 0) of std_logic_vector(7 downto 0);
11  type eFEX_mapping_array is array(15 downto 0) of std_logic_vector(3 downto 0);
12  constant eFEX_mapping: eFEX_mapping_array := (x"C", x"B", x"0", x"A", x"1", x"9", x"2", x"8", x"3", x"7", x"4", x"6", x"5", x"C", x"C", x"C"); -- Logical Slot Address to eFEX number
13 
14  -- Processors
15  function F_MGT_QUAD_ENABLE (fpga_number : in integer) return std_logic_vector;
16  function F_MGT_USE_OTHER_CLK_N (fpga_number : in integer) return integer;
17  function F_IPBUS_PORT_N (fpga_number : in integer) return std_logic_vector;
18  function F_MGT_USE_OTHER_CLK (fpga_number : in integer) return std_logic_vector;
19  function F_MGT_TX_POWER (fpga_number : in integer) return std_logic_vector;
20  function F_MGT_RX_POWER (fpga_number : in integer) return std_logic_vector;
21  function F_ENABLE_MERGING (fpga_number : in integer) return std_logic;
22 
23  function xadc_reg48 (fpga_number : in integer) return bit_vector;
24  function xadc_reg49 (fpga_number : in integer) return bit_vector;
25 
26  procedure MGT_SELECTOR_RX (
27  signal fpga_number : in integer;
28  signal in_BC_Reg_sel : in std_logic_vector(319 downto 0);
29  signal in_mux_sel : in std_logic_vector(319 downto 0);
30  signal in_delay_num : out std_logic_vector(319 downto 0);
31  signal in_bc_cntr_0 : out std_logic_vector(139 downto 0);
32  signal in_bc_cntr_1 : out std_logic_vector(139 downto 0);
33  signal in_bc_cntr_2 : out std_logic_vector(139 downto 0);
34  signal in_bc_cntr_3 : out std_logic_vector(139 downto 0);
35  signal in_bc_mux_cntr_0 : out std_logic_vector(139 downto 0);
36  signal in_bc_mux_cntr_1 : out std_logic_vector(139 downto 0);
37  signal in_bc_mux_cntr_2 : out std_logic_vector(139 downto 0);
38  signal in_bc_mux_cntr_3 : out std_logic_vector(139 downto 0);
39  signal in_mgt_RXUSRCLK_OUT : in std_logic_vector(79 downto 0);
40  signal in_enable_mgt : in std_logic_vector(79 downto 0);
41  signal in_bcn_synch : out std_logic_vector(79 downto 0);
42  signal in_crc_error_chan : out std_logic_vector(79 downto 0);
43  signal in_notable_error : in std_logic_vector(79 downto 0);
44  signal in_disperr_error : in std_logic_vector(79 downto 0);
45  signal in_rx_resetdone : in std_logic_vector(79 downto 0);
46  signal out_BC_Reg_sel : out std_logic_vector(255 downto 0);
47  signal out_mux_sel : out std_logic_vector(255 downto 0);
48  signal out_delay_num : in std_logic_vector(255 downto 0);
49  signal out_bc_cntr_0 : in std_logic_vector(111 downto 0);
50  signal out_bc_cntr_1 : in std_logic_vector(111 downto 0);
51  signal out_bc_cntr_2 : in std_logic_vector(111 downto 0);
52  signal out_bc_cntr_3 : in std_logic_vector(111 downto 0);
53  signal out_bc_mux_cntr_0 : in std_logic_vector(111 downto 0);
54  signal out_bc_mux_cntr_1 : in std_logic_vector(111 downto 0);
55  signal out_bc_mux_cntr_2 : in std_logic_vector(111 downto 0);
56  signal out_bc_mux_cntr_3 : in std_logic_vector(111 downto 0);
57  signal out_mgt_RXUSRCLK_OUT : out std_logic_vector(63 downto 0);
58  signal out_enable_mgt : out std_logic_vector(63 downto 0);
59  signal out_bcn_synch : in std_logic_vector(63 downto 0);
60  signal out_crc_error_chan : in std_logic_vector(63 downto 0);
61  signal out_disperr_error : out std_logic_vector(63 downto 0);
62  signal out_notable_error : out std_logic_vector(63 downto 0);
63 
64  signal out_rx_resetdone : out std_logic_vector(63 downto 0);
65  signal in_MGT_Commadet : in std_logic_vector(79 downto 0);
66  signal in_MGT_Data : in mgt_rxdata_array (19 downto 0);
67  signal out_MGT_Commadet : out std_logic_vector(63 downto 0);
68  signal out_MGT_Data : out mgt_rxdata_array (15 downto 0);
69 
70  signal in_rxdata_mgt0 : out std_logic_vector(639 downto 0);
71  signal in_rxdata_mgt1 : out std_logic_vector(639 downto 0);
72  signal in_rxdata_mgt2 : out std_logic_vector(639 downto 0);
73  signal in_rxdata_mgt3 : out std_logic_vector(639 downto 0);
74 
75  signal out_rxdata_mgt0 : in std_logic_vector(511 downto 0);
76  signal out_rxdata_mgt1 : in std_logic_vector(511 downto 0);
77  signal out_rxdata_mgt2 : in std_logic_vector(511 downto 0);
78  signal out_rxdata_mgt3 : in std_logic_vector(511 downto 0);
79 
80  signal in_ram_data_mgt0 : in std_logic_vector(4559 downto 0);
81  signal in_ram_data_mgt1 : in std_logic_vector(4559 downto 0);
82  signal in_ram_data_mgt2 : in std_logic_vector(4559 downto 0);
83  signal in_ram_data_mgt3 : in std_logic_vector(4559 downto 0);
84 
85  signal out_ram_data_mgt0 : out std_logic_vector(3647 downto 0);
86  signal out_ram_data_mgt1 : out std_logic_vector(3647 downto 0);
87  signal out_ram_data_mgt2 : out std_logic_vector(3647 downto 0);
88  signal out_ram_data_mgt3 : out std_logic_vector(3647 downto 0);
89 
90 
91  signal in_align_frame : in std_logic_vector(79 downto 0);
92  signal out_align_frame : out std_logic_vector(63 downto 0);
93 
94  signal in_kchar : in std_logic_vector(79 downto 0);
95  signal out_kchar : out std_logic_vector(63 downto 0)
96 
97 
98 
99  );
100 
101 
102  --signal in_mgt_TXUSRCLK_OUT : in std_logic_vector(11 downto 0); procedure MGT_SELECTOR_TX (
103  signal fpga_number : in integer;
104 
105  signal in_mgt_usr_clk : in std_logic_vector(79 downto 0);
106  signal in_txdata_0 : in std_logic_vector(33 downto 0);
107  signal in_txdata_1 : in std_logic_vector(33 downto 0);
108  signal in_txdata_2 : in std_logic_vector(33 downto 0);
109  signal in_txdata_3 : in std_logic_vector(33 downto 0);
110  signal in_txdata_4 : in std_logic_vector(33 downto 0);
111  signal in_txdata_5 : in std_logic_vector(33 downto 0);
112  signal in_txdata_6 : in std_logic_vector(33 downto 0);
113  signal in_txdata_7 : in std_logic_vector(33 downto 0);
114  signal in_txdata_8 : in std_logic_vector(33 downto 0);
115  signal in_txdata_9 : in std_logic_vector(33 downto 0);
116  signal in_txdata_10 : in std_logic_vector(33 downto 0);
117  signal in_txdata_11 : in std_logic_vector(33 downto 0);
118 
119 
120  signal in_topo_k : in std_logic;
121  signal in_raw_k : in std_logic;
122  signal in_topo_data : in std_logic_vector(31 downto 0);
123  signal in_raw_data : in std_logic_vector(31 downto 0);
124  signal out_topo_tob_clk : out std_logic;
125  signal out_topo_raw_clk : out std_logic;
126  signal out_mgt_usr_clk : out std_logic_vector(11 downto 0);
127  signal out_txcharisk_quad_array : out mgt_txcharisk_array(19 downto 0);
128 
129  signal out_txdata_quad_array : out mgt_txdata_array(19 downto 0)
130  );
131 
132 end package ProcessorFPGAPackage;
133 
134 package body ProcessorFPGAPackage is
135 
136 --- functions to configure MGTs for FPGA 1, 2, 3, and 4
137  function F_MGT_QUAD_ENABLE (fpga_number : in integer) return std_logic_vector is
138  variable V_MGT_QUAD_ENABLE : std_logic_vector(19 downto 0);
139  begin
140  if fpga_number = 1 then
141  V_MGT_QUAD_ENABLE := "0000"&"1111"&"1111"&"1111"&"1111"; -- there must be 4 zeroes
142  elsif fpga_number = 2 then
143  V_MGT_QUAD_ENABLE := "1110"&"1100"&"0111"&"1111"&"1111"; -- there must be 4 zeroes
144  elsif fpga_number = 3 then
145  V_MGT_QUAD_ENABLE := "1111"&"1011"&"1111"&"1110"&"0011"; -- there must be 4 zeroes
146  elsif fpga_number = 4 then
147  V_MGT_QUAD_ENABLE := "1111"&"0111"&"1111"&"1110"&"0011"; -- there must be 4 zeroes
148  else
149  V_MGT_QUAD_ENABLE := x"00000";
150  end if;
151  return V_MGT_QUAD_ENABLE;
152  end function F_MGT_QUAD_ENABLE;
153 
154  function F_MGT_USE_OTHER_CLK (fpga_number : in integer) return std_logic_vector is
155  variable V_MGT_USE_OTHER_CLK : std_logic_vector(19 downto 0);
156  begin
157  if fpga_number = 1 then
158  V_MGT_USE_OTHER_CLK := x"00400";
159  elsif fpga_number = 2 then
160  V_MGT_USE_OTHER_CLK := x"00400";
161  elsif fpga_number = 3 then
162  V_MGT_USE_OTHER_CLK := x"02000";
163  elsif fpga_number = 4 then
164  V_MGT_USE_OTHER_CLK := x"00100";
165  else
166  V_MGT_USE_OTHER_CLK := x"00000";
167  end if;
168  return V_MGT_USE_OTHER_CLK;
169  end function F_MGT_USE_OTHER_CLK;
170 
171  function F_MGT_USE_OTHER_CLK_N (fpga_number : in integer) return integer is
172  variable V_MGT_USE_OTHER_CLK_N : integer;
173  begin
174  if fpga_number = 1 then
175  V_MGT_USE_OTHER_CLK_N := 10;
176  elsif fpga_number = 2 then
177  V_MGT_USE_OTHER_CLK_N := 10;
178  elsif fpga_number = 3 then
179  V_MGT_USE_OTHER_CLK_N := 13;
180  elsif fpga_number = 4 then
181  V_MGT_USE_OTHER_CLK_N := 8;
182  else
183  V_MGT_USE_OTHER_CLK_N := 0;
184  end if;
185  return V_MGT_USE_OTHER_CLK_N;
186  end function F_MGT_USE_OTHER_CLK_N;
187 
188  function F_IPBUS_PORT_N (fpga_number : in integer) return std_logic_vector is
189  variable V_IPBUS_PORT_N : std_logic_vector(15 downto 0);
190  begin
191  if fpga_number = 1 then
192  V_IPBUS_PORT_N := x"C352";
193  elsif fpga_number = 2 then
194  V_IPBUS_PORT_N := x"C353";
195  elsif fpga_number = 3 then
196  V_IPBUS_PORT_N := x"C354";
197  elsif fpga_number = 4 then
198  V_IPBUS_PORT_N := x"C355";
199  else
200  V_IPBUS_PORT_N := x"0000";
201  end if;
202  return V_IPBUS_PORT_N;
203  end function F_IPBUS_PORT_N;
204 
205  function F_MGT_TX_POWER (fpga_number : in integer) return std_logic_vector is
206  variable V_MGT_TX_POWER : std_logic_vector(79 downto 0);
207  begin
208  if fpga_number = 1 then
209  V_MGT_TX_POWER := x"0000_00ff_f300_0000_0000";
210  elsif fpga_number = 2 then
211  V_MGT_TX_POWER := x"fff0_0000_0300_0000_0000";
212  elsif fpga_number = 3 then
213  V_MGT_TX_POWER := x"0000_0030_0000_0000_0000";
214  elsif fpga_number = 4 then
215  V_MGT_TX_POWER := x"0000_0000_0003_0000_0000";
216  else
217  V_MGT_TX_POWER := x"0000_0000_0000_0000_0000";
218  end if;
219  return V_MGT_TX_POWER;
220  end function F_MGT_TX_POWER;
221 
222  function F_MGT_RX_POWER (fpga_number : in integer) return std_logic_vector is
223  variable V_MGT_RX_POWER : std_logic_vector(79 downto 0);
224  begin
225  if fpga_number = 1 then
226  --V_MGT_RX_POWER:=x"0000_e0f8_20ff_ffff_ffff";
227  V_MGT_RX_POWER := x"0000_f0ff_f0ff_ffff_ffff";
228  elsif fpga_number = 2 then
229  --V_MGT_RX_POWER:=x"1ab0_0700_00ff_ffff_ffff";
230  V_MGT_RX_POWER := x"fff0_0f00_00ff_ffff_ffff";
231  elsif fpga_number = 3 then
232  --V_MGT_RX_POWER:=x"ffff_f003_39ff_fff0_0091";
233  V_MGT_RX_POWER := x"ffff_f00f_ffff_fff0_00ff";
234  elsif fpga_number = 4 then
235  --V_MGT_RX_POWER:=x"03ac_0fff_ff70_fff0_00ff";
236  V_MGT_RX_POWER := x"0fff_0fff_fff0_fff0_00ff";
237  else
238  V_MGT_RX_POWER := x"0000_0000_0000_0000_0000";
239  end if;
240  return V_MGT_RX_POWER;
241  end function F_MGT_RX_POWER;
242 
243  function F_ENABLE_MERGING (fpga_number : in integer) return std_logic is
244  variable V_ENABLE_MERGING : std_logic;
245  begin
246  if fpga_number = 1 then
247  V_ENABLE_MERGING := '1';
248  elsif fpga_number = 2 then
249  V_ENABLE_MERGING := '1';
250  elsif fpga_number = 3 then
251  V_ENABLE_MERGING := '0';
252  elsif fpga_number = 4 then
253  V_ENABLE_MERGING := '0';
254  else
255  V_ENABLE_MERGING := '0';
256  end if;
257  return V_ENABLE_MERGING;
258  end function F_ENABLE_MERGING;
259 
260  procedure MGT_SELECTOR_RX
261  (
262  signal fpga_number : in integer;
263  signal in_BC_Reg_sel : in std_logic_vector(319 downto 0);
264  signal in_mux_sel : in std_logic_vector(319 downto 0);
265  signal in_delay_num : out std_logic_vector(319 downto 0);
266  signal in_bc_cntr_0 : out std_logic_vector(139 downto 0);
267  signal in_bc_cntr_1 : out std_logic_vector(139 downto 0);
268  signal in_bc_cntr_2 : out std_logic_vector(139 downto 0);
269  signal in_bc_cntr_3 : out std_logic_vector(139 downto 0);
270  signal in_bc_mux_cntr_0 : out std_logic_vector(139 downto 0);
271  signal in_bc_mux_cntr_1 : out std_logic_vector(139 downto 0);
272  signal in_bc_mux_cntr_2 : out std_logic_vector(139 downto 0);
273  signal in_bc_mux_cntr_3 : out std_logic_vector(139 downto 0);
274  signal in_mgt_RXUSRCLK_OUT : in std_logic_vector(79 downto 0);
275  signal in_enable_mgt : in std_logic_vector(79 downto 0);
276  signal in_bcn_synch : out std_logic_vector(79 downto 0);
277  signal in_crc_error_chan : out std_logic_vector(79 downto 0);
278  signal in_notable_error : in std_logic_vector(79 downto 0);
279  signal in_disperr_error : in std_logic_vector(79 downto 0);
280  signal in_rx_resetdone : in std_logic_vector(79 downto 0);
281  signal out_BC_Reg_sel : out std_logic_vector(255 downto 0);
282  signal out_mux_sel : out std_logic_vector(255 downto 0);
283  signal out_delay_num : in std_logic_vector(255 downto 0);
284  signal out_bc_cntr_0 : in std_logic_vector(111 downto 0);
285  signal out_bc_cntr_1 : in std_logic_vector(111 downto 0);
286  signal out_bc_cntr_2 : in std_logic_vector(111 downto 0);
287  signal out_bc_cntr_3 : in std_logic_vector(111 downto 0);
288  signal out_bc_mux_cntr_0 : in std_logic_vector(111 downto 0);
289  signal out_bc_mux_cntr_1 : in std_logic_vector(111 downto 0);
290  signal out_bc_mux_cntr_2 : in std_logic_vector(111 downto 0);
291  signal out_bc_mux_cntr_3 : in std_logic_vector(111 downto 0);
292  signal out_mgt_RXUSRCLK_OUT : out std_logic_vector(63 downto 0);
293  signal out_enable_mgt : out std_logic_vector(63 downto 0);
294  signal out_bcn_synch : in std_logic_vector(63 downto 0);
295  signal out_crc_error_chan : in std_logic_vector(63 downto 0);
296  signal out_disperr_error : out std_logic_vector(63 downto 0);
297  signal out_notable_error : out std_logic_vector(63 downto 0);
298 
299  signal out_rx_resetdone : out std_logic_vector(63 downto 0);
300  signal in_MGT_Commadet : in std_logic_vector(79 downto 0);
301  signal in_MGT_Data : in mgt_rxdata_array (19 downto 0);
302  signal out_MGT_Commadet : out std_logic_vector(63 downto 0);
303  signal out_MGT_Data : out mgt_rxdata_array (15 downto 0);
304 
305  signal in_rxdata_mgt0 : out std_logic_vector(639 downto 0);
306  signal in_rxdata_mgt1 : out std_logic_vector(639 downto 0);
307  signal in_rxdata_mgt2 : out std_logic_vector(639 downto 0);
308  signal in_rxdata_mgt3 : out std_logic_vector(639 downto 0);
309 
310  signal out_rxdata_mgt0 : in std_logic_vector(511 downto 0);
311  signal out_rxdata_mgt1 : in std_logic_vector(511 downto 0);
312  signal out_rxdata_mgt2 : in std_logic_vector(511 downto 0);
313  signal out_rxdata_mgt3 : in std_logic_vector(511 downto 0);
314 
315  signal in_ram_data_mgt0 : in std_logic_vector(4559 downto 0);
316  signal in_ram_data_mgt1 : in std_logic_vector(4559 downto 0);
317  signal in_ram_data_mgt2 : in std_logic_vector(4559 downto 0);
318  signal in_ram_data_mgt3 : in std_logic_vector(4559 downto 0);
319 
320  signal out_ram_data_mgt0 : out std_logic_vector(3647 downto 0);
321  signal out_ram_data_mgt1 : out std_logic_vector(3647 downto 0);
322  signal out_ram_data_mgt2 : out std_logic_vector(3647 downto 0);
323  signal out_ram_data_mgt3 : out std_logic_vector(3647 downto 0);
324 
325  signal in_align_frame : in std_logic_vector(79 downto 0);
326  signal out_align_frame : out std_logic_vector(63 downto 0);
327 
328  signal in_kchar : in std_logic_vector(79 downto 0);
329  signal out_kchar : out std_logic_vector(63 downto 0)
330  ) is
331  ----------
332 --variables here
333  variable v_BC_Reg_sel : std_logic_vector(255 downto 0);
334  variable v_mux_sel : std_logic_vector(255 downto 0);
335  variable v_delay_num : std_logic_vector(319 downto 0);
336  variable v_bc_cntr_0 : std_logic_vector(139 downto 0);
337  variable v_bc_cntr_1 : std_logic_vector(139 downto 0);
338  variable v_bc_cntr_2 : std_logic_vector(139 downto 0);
339  variable v_bc_cntr_3 : std_logic_vector(139 downto 0);
340  variable v_bc_mux_cntr_0 : std_logic_vector(139 downto 0);
341  variable v_bc_mux_cntr_1 : std_logic_vector(139 downto 0);
342  variable v_bc_mux_cntr_2 : std_logic_vector(139 downto 0);
343  variable v_bc_mux_cntr_3 : std_logic_vector(139 downto 0);
344  variable v_mgt_RXUSRCLK_OUT : std_logic_vector(63 downto 0);
345  variable v_enable_mgt : std_logic_vector(63 downto 0);
346  variable v_bcn_synch : std_logic_vector(79 downto 0);
347  variable v_crc_error_chan : std_logic_vector(79 downto 0);
348  variable v_disperr_error : std_logic_vector(63 downto 0);
349  variable v_notable_error : std_logic_vector(63 downto 0);
350 
351  variable v_rx_resetdone : std_logic_vector(63 downto 0);
352 
353  variable v_rxdata_mgt0 : std_logic_vector(639 downto 0);
354  variable v_rxdata_mgt1 : std_logic_vector(639 downto 0);
355  variable v_rxdata_mgt2 : std_logic_vector(639 downto 0);
356  variable v_rxdata_mgt3 : std_logic_vector(639 downto 0);
357 
358  variable v_ram_data_mgt0 : std_logic_vector(3647 downto 0);
359  variable v_ram_data_mgt1 : std_logic_vector(3647 downto 0);
360  variable v_ram_data_mgt2 : std_logic_vector(3647 downto 0);
361  variable v_ram_data_mgt3 : std_logic_vector(3647 downto 0);
362  variable v_kchar : std_logic_vector(63 downto 0);
363  variable v_align_frame : std_logic_vector(63 downto 0);
364 
365 
366 
367  variable v_MGT_Commadet : std_logic_vector(63 downto 0);
368  variable v_MGT_Data : mgt_rxdata_array (15 downto 0);
369  variable m : integer := 1;
370  begin
371  -- in: 16-11 & 9-0 out: XXX 15-10 X 9-0
372  if fpga_number = 1 then
373  m := 1;
374  v_MGT_Data := in_MGT_Data(17*m - 1 downto 11*m) & in_MGT_Data(10*m - 1 downto 0);
375  m := 16;
376  v_BC_Reg_sel := in_BC_Reg_sel(17*m - 1 downto 11*m) & in_BC_Reg_sel(10*m - 1 downto 0);
377  v_mux_sel := in_mux_sel(17*m - 1 downto 11*m) & in_mux_sel(10*m - 1 downto 0);
378 
379  v_delay_num := x"0000_0000_0000" & out_delay_num(16*m - 1 downto 10*m) & x"0000" & out_delay_num(10*m - 1 downto 0);
380  m := 7;
381  v_bc_cntr_0 := "0000000"&"0000000"&"0000000" & out_bc_cntr_0(16*m - 1 downto 10*m) & "0000000" & out_bc_cntr_0(10*m - 1 downto 0);
382  v_bc_cntr_1 := "0000000"&"0000000"&"0000000" & out_bc_cntr_1(16*m - 1 downto 10*m) & "0000000" & out_bc_cntr_1(10*m - 1 downto 0);
383  v_bc_cntr_2 := "0000000"&"0000000"&"0000000" & out_bc_cntr_2(16*m - 1 downto 10*m) & "0000000" & out_bc_cntr_2(10*m - 1 downto 0);
384  v_bc_cntr_3 := "0000000"&"0000000"&"0000000" & out_bc_cntr_3(16*m - 1 downto 10*m) & "0000000" & out_bc_cntr_3(10*m - 1 downto 0);
385  v_bc_mux_cntr_0 := "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_0(16*m - 1 downto 10*m) & "0000000" & out_bc_mux_cntr_0(10*m - 1 downto 0);
386  v_bc_mux_cntr_1 := "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_1(16*m - 1 downto 10*m) & "0000000" & out_bc_mux_cntr_1(10*m - 1 downto 0);
387  v_bc_mux_cntr_2 := "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_2(16*m - 1 downto 10*m) & "0000000" & out_bc_mux_cntr_2(10*m - 1 downto 0);
388  v_bc_mux_cntr_3 := "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_3(16*m - 1 downto 10*m) & "0000000" & out_bc_mux_cntr_3(10*m - 1 downto 0);
389 
390  m := 32;
391  v_rxdata_mgt0 := x"0000000_00000000_000000000" & out_rxdata_mgt0(16*m - 1 downto 10*m) & x"00000000" & out_rxdata_mgt0(10*m - 1 downto 0);
392  v_rxdata_mgt1 := x"0000000_00000000_000000000" & out_rxdata_mgt1(16*m - 1 downto 10*m) & x"00000000" & out_rxdata_mgt1(10*m - 1 downto 0);
393  v_rxdata_mgt2 := x"0000000_00000000_000000000" & out_rxdata_mgt2(16*m - 1 downto 10*m) & x"00000000" & out_rxdata_mgt2(10*m - 1 downto 0);
394  v_rxdata_mgt3 := x"0000000_00000000_000000000" & out_rxdata_mgt3(16*m - 1 downto 10*m) & x"00000000" & out_rxdata_mgt3(10*m - 1 downto 0);
395 
396  m := 228;
397  v_ram_data_mgt0 := in_ram_data_mgt0(17*m - 1 downto 11*m) & in_ram_data_mgt0(10*m - 1 downto 0);
398  v_ram_data_mgt1 := in_ram_data_mgt1(17*m - 1 downto 11*m) & in_ram_data_mgt1(10*m - 1 downto 0);
399  v_ram_data_mgt2 := in_ram_data_mgt2(17*m - 1 downto 11*m) & in_ram_data_mgt2(10*m - 1 downto 0);
400  v_ram_data_mgt3 := in_ram_data_mgt3(17*m - 1 downto 11*m) & in_ram_data_mgt3(10*m - 1 downto 0);
401 
402  m := 4;
403  v_mgt_RXUSRCLK_OUT := in_mgt_RXUSRCLK_OUT(17*m - 1 downto 11*m) & in_mgt_RXUSRCLK_OUT(10*m - 1 downto 0);
404  v_disperr_error := in_disperr_error(17*m - 1 downto 11*m) & in_disperr_error(10*m - 1 downto 0);
405  v_notable_error := in_notable_error(17*m - 1 downto 11*m) & in_notable_error(10*m - 1 downto 0);
406 
407  v_bcn_synch := x"0_0_0" & out_bcn_synch(16*m - 1 downto 10*m) & x"0" & out_bcn_synch(10*m - 1 downto 0);
408  v_crc_error_chan := x"0_0_0" & out_crc_error_chan(16*m - 1 downto 10*m) & x"0" & out_crc_error_chan(10*m - 1 downto 0);
409  v_rx_resetdone := in_rx_resetdone(17*m - 1 downto 11*m) & in_rx_resetdone(10*m - 1 downto 0);
410  v_enable_mgt := in_enable_mgt(17*m - 1 downto 11*m) & in_enable_mgt(10*m - 1 downto 0);
411  v_MGT_Commadet := in_MGT_Commadet(17*m - 1 downto 11*m) & in_MGT_Commadet(10*m - 1 downto 0);
412  v_kchar := in_kchar (17*m - 1 downto 11*m) & in_kchar (10*m - 1 downto 0);
413  v_align_frame := in_align_frame (17*m - 1 downto 11*m) & in_align_frame(10*m - 1 downto 0);
414 
415 
416  -- in: 19-17 & 15-13 & 9-0 out: 15-13 X 12-10 XXX 9-0
417  elsif fpga_number = 2 then
418  m := 1;
419  v_MGT_Data := in_MGT_Data (20*m - 1 downto 17*m) & in_MGT_Data(16*m - 1 downto 13*m) & in_MGT_Data(10*m - 1 downto 0);
420  m := 16;
421  v_BC_Reg_sel := in_BC_Reg_sel (20*m - 1 downto 17*m) & in_BC_Reg_sel (16*m - 1 downto 13*m) & in_BC_Reg_sel (10*m - 1 downto 0);
422  v_mux_sel := in_mux_sel (20*m - 1 downto 17*m) & in_mux_sel (16*m - 1 downto 13*m) & in_mux_sel (10*m - 1 downto 0);
423 
424  v_delay_num := out_delay_num(16*m - 1 downto 13*m) & x"0000" & out_delay_num(13*m - 1 downto 10*m) & x"0000_0000_0000" & out_delay_num(10*m - 1 downto 0);
425  m := 7;
426  v_bc_cntr_0 := out_bc_cntr_0(16*m - 1 downto 13*m) & "0000000" & out_bc_cntr_0(13*m - 1 downto 10*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_0(10*m - 1 downto 0);
427  v_bc_cntr_1 := out_bc_cntr_1(16*m - 1 downto 13*m) & "0000000" & out_bc_cntr_1(13*m - 1 downto 10*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_1(10*m - 1 downto 0);
428  v_bc_cntr_2 := out_bc_cntr_2(16*m - 1 downto 13*m) & "0000000" & out_bc_cntr_2(13*m - 1 downto 10*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_2(10*m - 1 downto 0);
429  v_bc_cntr_3 := out_bc_cntr_3(16*m - 1 downto 13*m) & "0000000" & out_bc_cntr_3(13*m - 1 downto 10*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_3(10*m - 1 downto 0);
430  v_bc_mux_cntr_0 := out_bc_mux_cntr_0(16*m - 1 downto 13*m) & "0000000" & out_bc_mux_cntr_0(13*m - 1 downto 10*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_0(10*m - 1 downto 0);
431  v_bc_mux_cntr_1 := out_bc_mux_cntr_1(16*m - 1 downto 13*m) & "0000000" & out_bc_mux_cntr_1(13*m - 1 downto 10*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_1(10*m - 1 downto 0);
432  v_bc_mux_cntr_2 := out_bc_mux_cntr_2(16*m - 1 downto 13*m) & "0000000" & out_bc_mux_cntr_2(13*m - 1 downto 10*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_2(10*m - 1 downto 0);
433  v_bc_mux_cntr_3 := out_bc_mux_cntr_3(16*m - 1 downto 13*m) & "0000000" & out_bc_mux_cntr_3(13*m - 1 downto 10*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_3(10*m - 1 downto 0);
434 
435  m := 32;
436  v_rxdata_mgt0 := out_rxdata_mgt0(16*m - 1 downto 13*m) & x"00000000" & out_rxdata_mgt0(13*m - 1 downto 10*m) & x"00000000_00000000_00000000" & out_rxdata_mgt0(10*m - 1 downto 0);
437  v_rxdata_mgt1 := out_rxdata_mgt1(16*m - 1 downto 13*m) & x"00000000" & out_rxdata_mgt1(13*m - 1 downto 10*m) & x"00000000_00000000_00000000" & out_rxdata_mgt1(10*m - 1 downto 0);
438  v_rxdata_mgt2 := out_rxdata_mgt2(16*m - 1 downto 13*m) & x"00000000" & out_rxdata_mgt2(13*m - 1 downto 10*m) & x"00000000_00000000_00000000" & out_rxdata_mgt2(10*m - 1 downto 0);
439  v_rxdata_mgt3 := out_rxdata_mgt3(16*m - 1 downto 13*m) & x"00000000" & out_rxdata_mgt3(13*m - 1 downto 10*m) & x"00000000_00000000_00000000" & out_rxdata_mgt3(10*m - 1 downto 0);
440 
441  m := 228;
442  v_ram_data_mgt0 := in_ram_data_mgt0(20*m - 1 downto 17*m) & in_ram_data_mgt0(16*m - 1 downto 13*m) & in_ram_data_mgt0(10*m - 1 downto 0);
443  v_ram_data_mgt1 := in_ram_data_mgt1(20*m - 1 downto 17*m) & in_ram_data_mgt1(16*m - 1 downto 13*m) & in_ram_data_mgt1(10*m - 1 downto 0);
444  v_ram_data_mgt2 := in_ram_data_mgt2(20*m - 1 downto 17*m) & in_ram_data_mgt2(16*m - 1 downto 13*m) & in_ram_data_mgt2(10*m - 1 downto 0);
445  v_ram_data_mgt3 := in_ram_data_mgt3(20*m - 1 downto 17*m) & in_ram_data_mgt3(16*m - 1 downto 13*m) & in_ram_data_mgt3(10*m - 1 downto 0);
446 
447 
448  m := 4;
449  v_mgt_RXUSRCLK_OUT := in_mgt_RXUSRCLK_OUT (20*m - 1 downto 17*m) & in_mgt_RXUSRCLK_OUT (16*m - 1 downto 13*m) & in_mgt_RXUSRCLK_OUT (10*m - 1 downto 0);
450  v_disperr_error := in_disperr_error (20*m - 1 downto 17*m) & in_disperr_error (16*m - 1 downto 13*m) & in_disperr_error (10*m - 1 downto 0);
451  v_notable_error := in_notable_error (20*m - 1 downto 17*m) & in_notable_error (16*m - 1 downto 13*m) & in_notable_error(10*m - 1 downto 0);
452 
453  v_bcn_synch := out_bcn_synch(16*m - 1 downto 13*m) & x"0" & out_bcn_synch (13*m - 1 downto 10*m) & x"0_0_0" & out_bcn_synch(10*m - 1 downto 0);
454  v_crc_error_chan := out_crc_error_chan(16*m - 1 downto 13*m) & x"0" & out_crc_error_chan (13*m - 1 downto 10*m) & x"0_0_0" & out_crc_error_chan(10*m - 1 downto 0);
455  v_rx_resetdone := in_rx_resetdone (20*m - 1 downto 17*m) & in_rx_resetdone (16*m - 1 downto 13*m) & in_rx_resetdone (10*m - 1 downto 0);
456  v_enable_mgt := in_enable_mgt (20*m - 1 downto 17*m) & in_enable_mgt (16*m - 1 downto 13*m) & in_enable_mgt (10*m - 1 downto 0);
457  v_MGT_Commadet := in_MGT_Commadet (20*m - 1 downto 17*m) & in_MGT_Commadet (16*m - 1 downto 13*m) & in_MGT_Commadet (10*m - 1 downto 0);
458 
459  v_kchar := in_kchar (20*m - 1 downto 17*m) & in_kchar (16*m - 1 downto 13*m) & in_kchar (10*m - 1 downto 0);
460  v_align_frame := in_align_frame (20*m - 1 downto 17*m) & in_align_frame (16*m - 1 downto 13*m) & in_align_frame (10*m - 1 downto 0);
461 
462  -- in: 20-15 & 12-5 & 1-0 out: 15-10 XX 9-2 XXX 1-0
463  elsif fpga_number = 3 then
464 
465  m := 1;
466  v_MGT_Data := in_MGT_Data(20*m - 1 downto 14*m) & in_MGT_Data(13*m - 1 downto 5*m) & in_MGT_Data(2*m - 1 downto 0);
467  m := 16;
468  v_BC_Reg_sel := in_BC_Reg_sel (20*m - 1 downto 14*m) & in_BC_Reg_sel (13*m - 1 downto 5*m)& in_BC_Reg_sel (2*m - 1 downto 0);
469  v_mux_sel := in_mux_sel (20*m - 1 downto 14*m) & in_mux_sel (13*m - 1 downto 5*m)& in_mux_sel (2*m - 1 downto 0);
470 
471  v_delay_num := out_delay_num(16*m - 1 downto 10*m) & x"0000" & out_delay_num(10*m - 1 downto 2*m) & x"0000_0000_0000" & out_delay_num(2*m - 1 downto 0);
472  m := 7;
473  v_bc_cntr_0 := out_bc_cntr_0(16*m - 1 downto 10*m) & "0000000" & out_bc_cntr_0(10*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_0(2*m - 1 downto 0);
474  v_bc_cntr_1 := out_bc_cntr_1(16*m - 1 downto 10*m) & "0000000" & out_bc_cntr_1(10*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_1(2*m - 1 downto 0);
475  v_bc_cntr_2 := out_bc_cntr_2(16*m - 1 downto 10*m) & "0000000" & out_bc_cntr_2(10*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_2(2*m - 1 downto 0);
476  v_bc_cntr_3 := out_bc_cntr_3(16*m - 1 downto 10*m) & "0000000" & out_bc_cntr_3(10*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_3(2*m - 1 downto 0);
477  v_bc_mux_cntr_0 := out_bc_mux_cntr_0(16*m - 1 downto 10*m) & "0000000" & out_bc_mux_cntr_0(10*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_0(2*m - 1 downto 0);
478  v_bc_mux_cntr_1 := out_bc_mux_cntr_1(16*m - 1 downto 10*m) & "0000000" & out_bc_mux_cntr_1(10*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_1(2*m - 1 downto 0);
479  v_bc_mux_cntr_2 := out_bc_mux_cntr_2(16*m - 1 downto 10*m) & "0000000" & out_bc_mux_cntr_2(10*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_2(2*m - 1 downto 0);
480  v_bc_mux_cntr_3 := out_bc_mux_cntr_3(16*m - 1 downto 10*m) & "0000000" & out_bc_mux_cntr_3(10*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_3(2*m - 1 downto 0);
481 
482  m := 32;
483  v_rxdata_mgt0 := out_rxdata_mgt0(16*m - 1 downto 10*m) & x"00000000" & out_rxdata_mgt0(10*m - 1 downto 2*m) & x"00000000_00000000_00000000" & out_rxdata_mgt0(2*m - 1 downto 0);
484  v_rxdata_mgt1 := out_rxdata_mgt1(16*m - 1 downto 10*m) & x"00000000" & out_rxdata_mgt1(10*m - 1 downto 2*m) & x"00000000_00000000_00000000" & out_rxdata_mgt1(2*m - 1 downto 0);
485  v_rxdata_mgt2 := out_rxdata_mgt2(16*m - 1 downto 10*m) & x"00000000" & out_rxdata_mgt2(10*m - 1 downto 2*m) & x"00000000_00000000_00000000" & out_rxdata_mgt2(2*m - 1 downto 0);
486  v_rxdata_mgt3 := out_rxdata_mgt3(16*m - 1 downto 10*m) & x"00000000" & out_rxdata_mgt3(10*m - 1 downto 2*m) & x"00000000_00000000_00000000" & out_rxdata_mgt3(2*m - 1 downto 0);
487 
488  m := 228;
489  v_ram_data_mgt0 := in_ram_data_mgt0(20*m - 1 downto 14*m) & in_ram_data_mgt0(13*m - 1 downto 5*m) & in_ram_data_mgt0(2*m - 1 downto 0);
490  v_ram_data_mgt1 := in_ram_data_mgt1(20*m - 1 downto 14*m) & in_ram_data_mgt1(13*m - 1 downto 5*m) & in_ram_data_mgt1(2*m - 1 downto 0);
491  v_ram_data_mgt2 := in_ram_data_mgt2(20*m - 1 downto 14*m) & in_ram_data_mgt2(13*m - 1 downto 5*m) & in_ram_data_mgt2(2*m - 1 downto 0);
492  v_ram_data_mgt3 := in_ram_data_mgt3(20*m - 1 downto 14*m) & in_ram_data_mgt3(13*m - 1 downto 5*m) & in_ram_data_mgt3(2*m - 1 downto 0);
493 
494  m := 4;
495  v_mgt_RXUSRCLK_OUT := in_mgt_RXUSRCLK_OUT (20*m - 1 downto 14*m) & in_mgt_RXUSRCLK_OUT (13*m - 1 downto 5*m) & in_mgt_RXUSRCLK_OUT (2*m - 1 downto 0);
496  v_disperr_error := in_disperr_error (20*m - 1 downto 14*m) & in_disperr_error (13*m - 1 downto 5*m) & in_disperr_error (2*m - 1 downto 0);
497  v_notable_error := in_notable_error (20*m - 1 downto 14*m) & in_notable_error (13*m - 1 downto 5*m) & in_notable_error (2*m - 1 downto 0);
498 
499  v_bcn_synch := out_bcn_synch(16*m - 1 downto 10*m) & x"0" & out_bcn_synch (10*m - 1 downto 2*m) & x"0_0_0" & out_bcn_synch(2*m - 1 downto 0);
500  v_crc_error_chan := out_crc_error_chan(16*m - 1 downto 10*m) & x"0" & out_crc_error_chan (10*m - 1 downto 2*m) & x"0_0_0" & out_crc_error_chan(2*m - 1 downto 0);
501  v_rx_resetdone := in_rx_resetdone(20*m - 1 downto 14*m) & in_rx_resetdone (13*m - 1 downto 5*m) & in_rx_resetdone (2*m - 1 downto 0);
502 
503  v_enable_mgt := in_enable_mgt(20*m - 1 downto 14*m) & in_enable_mgt (13*m - 1 downto 5*m)&in_enable_mgt (2*m - 1 downto 0);
504  v_MGT_Commadet := in_MGT_Commadet(20*m - 1 downto 14*m) & in_MGT_Commadet (13*m - 1 downto 5*m) & in_MGT_Commadet (2*m - 1 downto 0);
505 
506  v_kchar := in_kchar(20*m - 1 downto 14*m) & in_kchar (13*m - 1 downto 5*m) & in_kchar (2*m - 1 downto 0);
507  v_align_frame := in_align_frame(20*m - 1 downto 14*m) & in_align_frame (13*m - 1 downto 5*m) & in_align_frame (2*m - 1 downto 0);
508 
509 -- in: 19-9 & 7-5 & 1-0 out: 15-5 X 4-2 XXX 1-0
510  elsif fpga_number = 4 then
511  m := 1;
512  v_MGT_Data := in_MGT_Data(20*m - 1 downto 9*m) & in_MGT_Data(8*m - 1 downto 5*m) & in_MGT_Data(2*m - 1 downto 0);
513  m := 16;
514  v_BC_Reg_sel := in_BC_Reg_sel (20*m - 1 downto 9*m) & in_BC_Reg_sel(8*m - 1 downto 5*m) & in_BC_Reg_sel (2*m - 1 downto 0);
515  v_mux_sel := in_mux_sel (20*m - 1 downto 9*m) & in_mux_sel(8*m - 1 downto 5*m) & in_mux_sel (2*m - 1 downto 0);
516 
517  v_delay_num := out_delay_num(16*m - 1 downto 5*m) & x"0000" & out_delay_num(5*m - 1 downto 2*m) & x"0000_0000_0000" & out_delay_num(2*m - 1 downto 0);
518  m := 7;
519  v_bc_cntr_0 := out_bc_cntr_0(16*m - 1 downto 5*m) & "0000000" & out_bc_cntr_0(5*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_0(2*m - 1 downto 0);
520  v_bc_cntr_1 := out_bc_cntr_1(16*m - 1 downto 5*m) & "0000000" & out_bc_cntr_1(5*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_1(2*m - 1 downto 0);
521  v_bc_cntr_2 := out_bc_cntr_2(16*m - 1 downto 5*m) & "0000000" & out_bc_cntr_2(5*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_2(2*m - 1 downto 0);
522  v_bc_cntr_3 := out_bc_cntr_3(16*m - 1 downto 5*m) & "0000000" & out_bc_cntr_3(5*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_cntr_3(2*m - 1 downto 0);
523  v_bc_mux_cntr_0 := out_bc_mux_cntr_0(16*m - 1 downto 5*m) & "0000000" & out_bc_mux_cntr_0(5*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_0(2*m - 1 downto 0);
524  v_bc_mux_cntr_1 := out_bc_mux_cntr_1(16*m - 1 downto 5*m) & "0000000" & out_bc_mux_cntr_1(5*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_1(2*m - 1 downto 0);
525  v_bc_mux_cntr_2 := out_bc_mux_cntr_2(16*m - 1 downto 5*m) & "0000000" & out_bc_mux_cntr_2(5*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_2(2*m - 1 downto 0);
526  v_bc_mux_cntr_3 := out_bc_mux_cntr_3(16*m - 1 downto 5*m) & "0000000" & out_bc_mux_cntr_3(5*m - 1 downto 2*m) & "0000000"&"0000000"&"0000000" & out_bc_mux_cntr_3(2*m - 1 downto 0);
527 
528  m := 32;
529  v_rxdata_mgt0 := out_rxdata_mgt0(16*m - 1 downto 5*m) & x"00000000" & out_rxdata_mgt0(5*m - 1 downto 2*m) & x"00000000_00000000_00000000" & out_rxdata_mgt0(2*m - 1 downto 0);
530  v_rxdata_mgt1 := out_rxdata_mgt1(16*m - 1 downto 5*m) & x"00000000" & out_rxdata_mgt1(5*m - 1 downto 2*m) & x"00000000_00000000_00000000" & out_rxdata_mgt1(2*m - 1 downto 0);
531  v_rxdata_mgt2 := out_rxdata_mgt2(16*m - 1 downto 5*m) & x"00000000" & out_rxdata_mgt2(5*m - 1 downto 2*m) & x"00000000_00000000_00000000" & out_rxdata_mgt2(2*m - 1 downto 0);
532  v_rxdata_mgt3 := out_rxdata_mgt3(16*m - 1 downto 5*m) & x"00000000" & out_rxdata_mgt3(5*m - 1 downto 2*m) & x"00000000_00000000_00000000" & out_rxdata_mgt3(2*m - 1 downto 0);
533 
534  m := 228;
535  v_ram_data_mgt0 := in_ram_data_mgt0(20*m - 1 downto 9*m) & in_ram_data_mgt0(8*m - 1 downto 5*m) & in_ram_data_mgt0(2*m - 1 downto 0);
536  v_ram_data_mgt1 := in_ram_data_mgt1(20*m - 1 downto 9*m) & in_ram_data_mgt1(8*m - 1 downto 5*m) & in_ram_data_mgt1(2*m - 1 downto 0);
537  v_ram_data_mgt2 := in_ram_data_mgt2(20*m - 1 downto 9*m) & in_ram_data_mgt2(8*m - 1 downto 5*m) & in_ram_data_mgt2(2*m - 1 downto 0);
538  v_ram_data_mgt3 := in_ram_data_mgt3(20*m - 1 downto 9*m) & in_ram_data_mgt3(8*m - 1 downto 5*m) & in_ram_data_mgt3(2*m - 1 downto 0);
539 
540  m := 4;
541  v_mgt_RXUSRCLK_OUT := in_mgt_RXUSRCLK_OUT (20*m - 1 downto 9*m) & in_mgt_RXUSRCLK_OUT(8*m - 1 downto 5*m) & in_mgt_RXUSRCLK_OUT(2*m - 1 downto 0);
542  v_disperr_error := in_disperr_error (20*m - 1 downto 9*m) & in_disperr_error(8*m - 1 downto 5*m) & in_disperr_error(2*m - 1 downto 0);
543  v_notable_error := in_notable_error (20*m - 1 downto 9*m) & in_notable_error(8*m - 1 downto 5*m) & in_notable_error(2*m - 1 downto 0);
544 
545  v_bcn_synch := out_bcn_synch(16*m - 1 downto 5*m) & x"0" & out_bcn_synch (5*m - 1 downto 2*m) & x"0_0_0" & out_bcn_synch(2*m - 1 downto 0);
546  v_crc_error_chan := out_crc_error_chan(16*m - 1 downto 5*m) & x"0" & out_crc_error_chan (5*m - 1 downto 2*m) & x"0_0_0" & out_crc_error_chan(2*m - 1 downto 0);
547 
548  v_rx_resetdone := in_rx_resetdone (20*m - 1 downto 9*m) & in_rx_resetdone(8*m - 1 downto 5*m) & in_rx_resetdone (2*m - 1 downto 0);
549 
550  v_enable_mgt := in_enable_mgt (20*m - 1 downto 9*m) & in_enable_mgt(8*m - 1 downto 5*m) & in_enable_mgt (2*m - 1 downto 0);
551  v_MGT_Commadet := in_MGT_Commadet (20*m - 1 downto 9*m) & in_MGT_Commadet(8*m - 1 downto 5*m) & in_MGT_Commadet (2*m - 1 downto 0);
552 
553  v_kchar := in_kchar (20*m - 1 downto 9*m) & in_kchar(8*m - 1 downto 5*m) & in_kchar (2*m - 1 downto 0);
554  v_align_frame := in_align_frame (20*m - 1 downto 9*m) & in_align_frame(8*m - 1 downto 5*m) & in_align_frame (2*m - 1 downto 0);
555 
556  end if;
557 
558  out_BC_Reg_sel <= v_BC_Reg_sel;
559  out_mux_sel <= v_mux_sel;
560  in_delay_num <= v_delay_num;
561  in_bc_cntr_0 <= v_bc_cntr_0;
562  in_bc_cntr_1 <= v_bc_cntr_1;
563  in_bc_cntr_2 <= v_bc_cntr_2;
564  in_bc_cntr_3 <= v_bc_cntr_3;
565  in_bc_mux_cntr_0 <= v_bc_mux_cntr_0;
566  in_bc_mux_cntr_1 <= v_bc_mux_cntr_1;
567  in_bc_mux_cntr_2 <= v_bc_mux_cntr_2;
568  in_bc_mux_cntr_3 <= v_bc_mux_cntr_3;
569  out_mgt_RXUSRCLK_OUT <= v_mgt_RXUSRCLK_OUT;
570  out_enable_mgt <= v_enable_mgt;
571  in_bcn_synch <= v_bcn_synch;
572  in_crc_error_chan <= v_crc_error_chan;
573  out_disperr_error <= v_disperr_error;
574  out_notable_error <= v_notable_error;
575  out_rx_resetdone <= v_rx_resetdone;
576  out_MGT_Commadet <= v_MGT_Commadet;
577  out_MGT_Data <= v_MGT_Data;
578 
579  in_rxdata_mgt0 <= v_rxdata_mgt0;
580  in_rxdata_mgt1 <= v_rxdata_mgt1;
581  in_rxdata_mgt2 <= v_rxdata_mgt2;
582  in_rxdata_mgt3 <= v_rxdata_mgt3;
583 
584  out_kchar <= v_kchar;
585  out_align_frame <= v_align_frame;
586 
587  out_ram_data_mgt0 <= v_ram_data_mgt0;
588  out_ram_data_mgt1 <= v_ram_data_mgt1;
589  out_ram_data_mgt2 <= v_ram_data_mgt2;
590  out_ram_data_mgt3 <= v_ram_data_mgt3;
591 
592  end MGT_SELECTOR_RX;
593 
594 
595 
596  procedure MGT_SELECTOR_TX (
597  signal fpga_number : in integer;
598 
599  signal in_mgt_usr_clk : in std_logic_vector(79 downto 0);
600 
601  signal in_txdata_0 : in std_logic_vector(33 downto 0);
602  signal in_txdata_1 : in std_logic_vector(33 downto 0);
603  signal in_txdata_2 : in std_logic_vector(33 downto 0);
604  signal in_txdata_3 : in std_logic_vector(33 downto 0);
605  signal in_txdata_4 : in std_logic_vector(33 downto 0);
606  signal in_txdata_5 : in std_logic_vector(33 downto 0);
607  signal in_txdata_6 : in std_logic_vector(33 downto 0);
608  signal in_txdata_7 : in std_logic_vector(33 downto 0);
609  signal in_txdata_8 : in std_logic_vector(33 downto 0);
610  signal in_txdata_9 : in std_logic_vector(33 downto 0);
611  signal in_txdata_10 : in std_logic_vector(33 downto 0);
612  signal in_txdata_11 : in std_logic_vector(33 downto 0);
613 
614 
615  signal in_topo_k : in std_logic;
616  signal in_raw_k : in std_logic;
617  signal in_topo_data : in std_logic_vector(31 downto 0);
618  signal in_raw_data : in std_logic_vector(31 downto 0);
619 
620  signal out_topo_tob_clk : out std_logic;
621  signal out_topo_raw_clk : out std_logic;
622  signal out_mgt_usr_clk : out std_logic_vector(11 downto 0);
623 
624  signal out_txcharisk_quad_array : out mgt_txcharisk_array(19 downto 0);
625  signal out_txdata_quad_array : out mgt_txdata_array(19 downto 0)
626 
627  ) is
628 
629  variable v_txcharisk_quad_array : mgt_txcharisk_array(19 downto 0) := (others => ZERO_MGT_TXCHARISK);
630  variable v_txdata_quad_array : mgt_txdata_array(19 downto 0) := (others => ZERO_MGT_TXDATA);
631 
632  variable v_topo_tob_clk : std_logic := '0';
633  variable v_topo_raw_clk : std_logic := '0';
634  variable v_mgt_usr_clk : std_logic_vector(11 downto 0) := (others => '0');
635 
636 
637  begin
638 
639  --210(first 2),211,212,213
640  if fpga_number = 1 then --111,112,210(first 2 SLOW),211 (prototype)
641  v_txcharisk_quad_array(10).gt0_txcharisk := "000"& in_topo_k;
642  v_txcharisk_quad_array(10).gt1_txcharisk := "000"& in_raw_k;
643 
644  v_txcharisk_quad_array(11).gt0_txcharisk := "000"& in_txdata_0(32);
645  v_txcharisk_quad_array(11).gt1_txcharisk := "000"& in_txdata_1(32);
646  v_txcharisk_quad_array(11).gt2_txcharisk := "000"& in_txdata_2(32);
647  v_txcharisk_quad_array(11).gt3_txcharisk := "000"& in_txdata_3(32);
648  v_txcharisk_quad_array(12).gt0_txcharisk := "000"& in_txdata_4(32);
649  v_txcharisk_quad_array(12).gt1_txcharisk := "000"& in_txdata_5(32);
650  v_txcharisk_quad_array(12).gt2_txcharisk := "000"& in_txdata_6(32);
651  v_txcharisk_quad_array(12).gt3_txcharisk := "000"& in_txdata_7(32);
652  v_txcharisk_quad_array(13).gt0_txcharisk := "000"& in_txdata_8(32);
653  v_txcharisk_quad_array(13).gt1_txcharisk := "000"& in_txdata_9(32);
654  v_txcharisk_quad_array(13).gt2_txcharisk := "000"& in_txdata_10(32);
655  v_txcharisk_quad_array(13).gt3_txcharisk := "000"& in_txdata_11(32);
656 
657  v_txdata_quad_array(10).gt0_txdata_in := in_topo_data;
658  v_txdata_quad_array(10).gt1_txdata_in := in_raw_data;
659 
660  v_txdata_quad_array(11).gt0_txdata_in := in_txdata_0(31 downto 0);
661  v_txdata_quad_array(11).gt1_txdata_in := in_txdata_1(31 downto 0);
662  v_txdata_quad_array(11).gt2_txdata_in := in_txdata_2(31 downto 0);
663  v_txdata_quad_array(11).gt3_txdata_in := in_txdata_3(31 downto 0);
664  v_txdata_quad_array(12).gt0_txdata_in := in_txdata_4(31 downto 0);
665  v_txdata_quad_array(12).gt1_txdata_in := in_txdata_5(31 downto 0);
666  v_txdata_quad_array(12).gt2_txdata_in := in_txdata_6(31 downto 0);
667  v_txdata_quad_array(12).gt3_txdata_in := in_txdata_7(31 downto 0);
668  v_txdata_quad_array(13).gt0_txdata_in := in_txdata_8(31 downto 0);
669  v_txdata_quad_array(13).gt1_txdata_in := in_txdata_9(31 downto 0);
670  v_txdata_quad_array(13).gt2_txdata_in := in_txdata_10(31 downto 0);
671  v_txdata_quad_array(13).gt3_txdata_in := in_txdata_11(31 downto 0);
672 
673  v_topo_raw_clk := in_mgt_usr_clk(41);
674  v_topo_tob_clk := in_mgt_usr_clk(40);
675  -- 13 12 11
676  v_mgt_usr_clk := in_mgt_usr_clk(13*4+3 downto 13*4) & in_mgt_usr_clk(12*4+3 downto 12*4) & in_mgt_usr_clk(11*4+3 downto 11*4);
677 
678  elsif fpga_number = 2 then --210(first 2),217,218,219
679  --119,210(first 2 SLOW),217,218 (prototype)
680 
681  v_txcharisk_quad_array(10).gt0_txcharisk := "000"& in_topo_k;
682  v_txcharisk_quad_array(10).gt1_txcharisk := "000"& in_raw_k;
683 
684  v_txcharisk_quad_array(17).gt0_txcharisk := "000"& in_txdata_0(32);
685  v_txcharisk_quad_array(17).gt1_txcharisk := "000"& in_txdata_1(32);
686  v_txcharisk_quad_array(17).gt2_txcharisk := "000"& in_txdata_2(32);
687  v_txcharisk_quad_array(17).gt3_txcharisk := "000"& in_txdata_3(32);
688 
689  v_txcharisk_quad_array(18).gt0_txcharisk := "000"& in_txdata_4(32);
690  v_txcharisk_quad_array(18).gt1_txcharisk := "000"& in_txdata_5(32);
691  v_txcharisk_quad_array(18).gt2_txcharisk := "000"& in_txdata_6(32);
692  v_txcharisk_quad_array(18).gt3_txcharisk := "000"& in_txdata_7(32);
693  v_txcharisk_quad_array(19).gt0_txcharisk := "000"& in_txdata_8(32);
694  v_txcharisk_quad_array(19).gt1_txcharisk := "000"& in_txdata_9(32);
695  v_txcharisk_quad_array(19).gt2_txcharisk := "000"& in_txdata_10(32);
696  v_txcharisk_quad_array(19).gt3_txcharisk := "000"& in_txdata_11(32);
697 
698  v_txdata_quad_array(10).gt0_txdata_in := in_topo_data;
699  v_txdata_quad_array(10).gt1_txdata_in := in_raw_data;
700 
701  v_txdata_quad_array(17).gt0_txdata_in := in_txdata_0(31 downto 0);
702  v_txdata_quad_array(17).gt1_txdata_in := in_txdata_1(31 downto 0);
703  v_txdata_quad_array(17).gt2_txdata_in := in_txdata_2(31 downto 0);
704  v_txdata_quad_array(17).gt3_txdata_in := in_txdata_3(31 downto 0);
705  v_txdata_quad_array(18).gt0_txdata_in := in_txdata_4(31 downto 0);
706  v_txdata_quad_array(18).gt1_txdata_in := in_txdata_5(31 downto 0);
707  v_txdata_quad_array(18).gt2_txdata_in := in_txdata_6(31 downto 0);
708  v_txdata_quad_array(18).gt3_txdata_in := in_txdata_7(31 downto 0);
709  v_txdata_quad_array(19).gt0_txdata_in := in_txdata_8(31 downto 0);
710  v_txdata_quad_array(19).gt1_txdata_in := in_txdata_9(31 downto 0);
711  v_txdata_quad_array(19).gt2_txdata_in := in_txdata_10(31 downto 0);
712  v_txdata_quad_array(19).gt3_txdata_in := in_txdata_11(31 downto 0);
713 
714  v_topo_raw_clk := in_mgt_usr_clk(41);
715  v_topo_tob_clk := in_mgt_usr_clk(40);
716  -- 19 18 17
717  v_mgt_usr_clk := in_mgt_usr_clk(19*4+3 downto 19*4) & in_mgt_usr_clk(18*4+3 downto 18*4) & in_mgt_usr_clk(17*4+3 downto 17*4);
718 
719  elsif fpga_number = 3 then --first 2 MGTs of quad 213 (same as prototype)
720  v_txcharisk_quad_array(13).gt0_txcharisk := "000"& in_topo_k;
721  v_txcharisk_quad_array(13).gt1_txcharisk := "000"& in_raw_k;
722 
723  v_txdata_quad_array(13).gt0_txdata_in := in_topo_data;
724  v_txdata_quad_array(13).gt1_txdata_in := in_raw_data;
725 
726  v_mgt_usr_clk := (others => '0');
727  v_topo_raw_clk := in_mgt_usr_clk(53);
728  v_topo_tob_clk := in_mgt_usr_clk(52);
729 
730  elsif fpga_number = 4 then --first 2 MGTs of quad 118 (same as prototype
731  v_txcharisk_quad_array(8).gt0_txcharisk := "000"& in_topo_k;
732  v_txcharisk_quad_array(8).gt1_txcharisk := "000"& in_raw_k;
733 
734  v_txdata_quad_array(8).gt0_txdata_in := in_topo_data;
735  v_txdata_quad_array(8).gt1_txdata_in := in_raw_data;
736 
737  v_mgt_usr_clk := (others => '0');
738  v_topo_raw_clk := in_mgt_usr_clk(33);
739  v_topo_tob_clk := in_mgt_usr_clk(32);
740 
741  else
742  --do something here
743  v_mgt_usr_clk := (others => '0');
744 
745  end if;
746  out_txcharisk_quad_array <= v_txcharisk_quad_array;
747  out_txdata_quad_array <= v_txdata_quad_array;
748  out_topo_tob_clk <= v_topo_tob_clk;
749  out_topo_raw_clk <= v_topo_raw_clk;
750  out_mgt_usr_clk <= v_mgt_usr_clk;
751  end MGT_SELECTOR_TX;
752 
753 
754 
755  ---xadc functions for reg 48 and reg 49
756 function xadc_reg48(fpga_number : in integer) return bit_vector is
757  variable init_reg48: bit_vector(15 downto 0);
758  begin
759  if fpga_number = 1 or fpga_number = 2 then
760  init_reg48 := x"4701";
761  elsif fpga_number = 3 or fpga_number = 4 then
762  init_reg48 := x"4f01";
763  else
764  init_reg48 := x"4f01";
765  end if;
766  return init_reg48;
767  end function xadc_reg48;
768 
769  function xadc_reg49(fpga_number : in integer) return bit_vector is
770  variable init_reg49: bit_vector(15 downto 0);
771  begin
772  if fpga_number = 1 or fpga_number = 2 then
773  init_reg49 := x"0000";
774  elsif fpga_number = 3 or fpga_number = 4 then
775  init_reg49 := x"0001";
776  else
777  init_reg49 := x"050f";
778  end if;
779  return init_reg49;
780  end function xadc_reg49;
781 
782 
783 
784 
785 end ProcessorFPGAPackage;
mgt_type
Definition: mgt_type_pkg.vhd:4
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