proc_FPGAs Entity Reference

process FPGA ipbus connection More...

Inheritance diagram for proc_FPGAs:

Entities
Behavioral	architecture
	process FPGA ipbus connection More...

Libraries
IEEE
work
ipbus_lib

Use Clauses
STD_LOGIC_1164
ipbus
ipbus_trans_decl
mac_arbiter_decl

Generics
IPBUSPORT	std_logic_vector ( 15 DOWNTO 0 )

Ports
ipb_clk	in	std_logic
		IPBus clock of 31.25MHz.
mac_clk	in	std_logic
		clock 125 MHz
rst_ipb	in	std_logic
		IPBus Reset input.
rst_macclk	in	std_logic
		macclk Reset input
ipb_in	in	ipb_rbus
		IPBus input bus going from master to slaves.
ipb_out	out	ipb_wbus
		IPBus output bus going from slaves to master.
master_rx_data	in	std_logic_vector ( 9 DOWNTO 0 )
		IPBUS signals of master rx_data from control FPGA.
force_rx_error	in	std_logic
		Disable incoming rx_data from control FPGA.
master_tx_pause	in	std_logic
		IPBUS signals of master_tx_pause from control FPGA.
master_tx_data	out	std_logic_vector ( 9 DOWNTO 0 )
		IPBUS signals of master tx_data to control FPGA.

Detailed Description

process FPGA ipbus connection

This is the top level of the IPBUS control to the proccess FPGAs. There are 3 sections in this block: 1.udp slave if .

• Inter FPGA protocol is as follows:
• A frame is defined from first valid data until last is asserted (i.e. no explicit BOF)
• Format of the data between the FPGA is 8 bit data & 1 bit valid
• Valid set to 1 implies valid data, valid set to 0 that the data are a K character as below
• Valid data are put into a FIFO and if a K character is sent the next tick then this is
• used to assert last and error (corresponding to tuser in the AXI MAC) as follows:
• K28.0 => last
• K28.2 => last and error
• If err is asserted during a frame error is automatically asserted at the end of the frame
• Idle is indicated by K28.1 and K28.5
• By default K28.5 is used, but in the direction from slave to master K28.1 is used to signify
• Got_IP_addr set to 0
• N.B. assumption is that no other K chars are used so tests on K chars are not exhaustive
• HGFEDCBA
• K28.0 "00011100"
• K28.1 "00111100"
• K28.2 "01011100"
• K28.5 "10111100" This version selects the addressed slave depending on the state of incoming control lines.

2.Interconnectins of master rx and master tx to the control .

• This block generates even parity of the data and adds to tx data.
• It also performs parity check to the rx data from the control FPGA

3.Ipbus cntrl.

• This is top level of the ipbus bus master
• it bridges ethernet MAC interface and / or out-of-band interfaces to the ipbus

Author

Mohammed Siyad

Definition at line 45 of file Process_FPGA_IPbus.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/Process_FPGA_IPbus.vhd