38 use IEEE.STD_LOGIC_1164.
ALL;
41 USE ipbus_lib.ipbus.
all;
42 USE ipbus_lib.ipbus_trans_decl.
all;
43 USE ipbus_lib.mac_arbiter_decl.
all;
46 GENERIC(IPBUSPORT : std_logic_vector(15 DOWNTO 0));
77 SIGNAL actual_ip_addr : std_logic_vector(31 DOWNTO 0);
78 SIGNAL actual_mac_addr : std_logic_vector(47 DOWNTO 0);
79 SIGNAL IP_addr : std_logic_vector(31 DOWNTO 0);
80 SIGNAL MAC_addr : std_logic_vector(47 DOWNTO 0);
81 SIGNAL RARP : std_logic;
82 SIGNAL Remote_Got_IP_addr: std_logic;
83 SIGNAL enable : std_logic;
84 SIGNAL ipb_grant : std_logic := '1';
86 SIGNAL mac_rx_data : std_logic_vector(7 DOWNTO 0);
87 SIGNAL mac_rx_error, mac_rx_last,mac_rx_valid : std_logic;
88 SIGNAL slave_rx_data : std_logic_vector(8 DOWNTO 0);
89 SIGNAL slave_rx_err, node_rx_err : std_logic;
91 SIGNAL mac_tx_data : std_logic_vector(7 DOWNTO 0);
92 SIGNAL mac_tx_error,mac_tx_last,mac_tx_ready,mac_tx_valid : std_logic;
93 SIGNAL slave_tx_data : std_logic_vector(8 DOWNTO 0);
98 IP_addr <= (others =>'0');
99 MAC_addr <= (others =>'0');
107 U_0 :
entity ipbus_lib.UDP_node_if
111 mac_rx_data => mac_rx_data,
112 mac_rx_error => mac_rx_error,
113 mac_rx_last => mac_rx_last,
114 mac_rx_valid => mac_rx_valid,
115 Got_IP_addr => Remote_Got_IP_addr,
116 mac_tx_ready => mac_tx_ready,
117 mac_tx_data => mac_tx_data,
118 mac_tx_error => mac_tx_error,
119 mac_tx_last => mac_tx_last,
120 mac_tx_valid => mac_tx_valid,
121 node_rx_data => slave_rx_data,
122 node_rx_err => node_rx_err,
124 node_tx_data => slave_tx_data
137 U_2 :
entity ipbus_lib.ipbus_ctrl
151 SECONDARYPORT => '1',
162 mac_rx_data => mac_rx_data,
163 mac_rx_valid => mac_rx_valid,
164 mac_rx_last => mac_rx_last,
165 mac_rx_error => mac_rx_error,
166 mac_tx_data => mac_tx_data,
167 mac_tx_valid => mac_tx_valid,
168 mac_tx_last => mac_tx_last,
169 mac_tx_error => mac_tx_error,
170 mac_tx_ready => mac_tx_ready,
174 ipb_grant => ipb_grant,
175 mac_addr => MAC_addr,
177 ipbus_port => IPBUSPORT,
180 actual_mac_addr => actual_mac_addr,
181 actual_ip_addr => actual_ip_addr,
182 Got_IP_addr => Remote_Got_IP_addr,
Top ipbus interconnection.
out rx_data std_logic_vector( 8 DOWNTO 0)
slave_rx_data
in mac_clk std_logic
clock 125 MHz
in master_rx_data std_logic_vector( 9 DOWNTO 0)
IPBUS signals of master rx_data from control FPGA.
in tx_data std_logic_vector( 8 DOWNTO 0)
slave_tx_data
out master_rx_err std_logic
parity error
in rst_macclk std_logic
macclk Reset input
out process_tx_data std_logic_vector( 9 DOWNTO 0)
master_tx_data
process FPGA ipbus connection
process FPGA ipbus connection
in master_tx_pause std_logic
IPBUS signals of master_tx_pause from control FPGA.
out ipb_out ipb_wbus
IPBus output bus going from slaves to master.
in ipb_in ipb_rbus
IPBus input bus going from master to slaves.
in mac_clk std_logic
clock 125 MHz
in force_rx_error std_logic
Disable incoming rx_data from control FPGA.
in master_rx_data std_logic_vector( 9 DOWNTO 0)
IPBUS signals of master rx_data from control FPGA.
in rst_ipb std_logic
IPBus Reset input.
out master_tx_data std_logic_vector( 9 DOWNTO 0)
IPBUS signals of master tx_data to control FPGA.
in ipb_clk std_logic
IPBus clock of 31.25MHz.
in rst_macclk std_logic
macclk Reset input