eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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Process_FPGA_IPbus.vhd
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1 
35 
36 
37 library IEEE;
38 use IEEE.STD_LOGIC_1164.ALL;
39 LIBRARY work;
40 library ipbus_lib;
41 USE ipbus_lib.ipbus.all;
42 USE ipbus_lib.ipbus_trans_decl.all;
43 USE ipbus_lib.mac_arbiter_decl.all;
45 entity proc_FPGAs is
46  GENERIC(IPBUSPORT : std_logic_vector(15 DOWNTO 0));
47  PORT(
49  ipb_clk : IN std_logic;
51  mac_clk : IN std_logic;
53  rst_ipb : IN std_logic;
55  rst_macclk : IN std_logic;
57  ipb_in : IN ipb_rbus;
59  ipb_out : OUT ipb_wbus;
61  master_rx_data : IN std_logic_vector (9 DOWNTO 0);
63  force_rx_error : IN std_logic;
65  master_tx_pause : IN std_logic;
67  master_tx_data : OUT std_logic_vector (9 DOWNTO 0)
68 
69 );
70 
71 end proc_FPGAs;
73 
74 architecture Behavioral of proc_FPGAs is
75 
76 
77 SIGNAL actual_ip_addr : std_logic_vector(31 DOWNTO 0);
78 SIGNAL actual_mac_addr : std_logic_vector(47 DOWNTO 0);
79 SIGNAL IP_addr : std_logic_vector(31 DOWNTO 0);
80 SIGNAL MAC_addr : std_logic_vector(47 DOWNTO 0);
81 SIGNAL RARP : std_logic;
82 SIGNAL Remote_Got_IP_addr: std_logic;
83 SIGNAL enable : std_logic;
84 SIGNAL ipb_grant : std_logic := '1';
85 
86 SIGNAL mac_rx_data : std_logic_vector(7 DOWNTO 0);
87 SIGNAL mac_rx_error, mac_rx_last,mac_rx_valid : std_logic;
88 SIGNAL slave_rx_data : std_logic_vector(8 DOWNTO 0);
89 SIGNAL slave_rx_err, node_rx_err : std_logic;
90 
91 SIGNAL mac_tx_data : std_logic_vector(7 DOWNTO 0);
92 SIGNAL mac_tx_error,mac_tx_last,mac_tx_ready,mac_tx_valid : std_logic;
93 SIGNAL slave_tx_data : std_logic_vector(8 DOWNTO 0);
94 
95 
96 BEGIN
97 
98  IP_addr <= (others =>'0');
99  MAC_addr <= (others =>'0');
100  Enable <= '1';
101  RARP <= '1';
102  ipb_grant <='1';
103 
104  node_rx_err <= slave_rx_err or force_rx_error; -- force bad packet if either parity error or override
105 
106 
107  U_0 :entity ipbus_lib.UDP_node_if
108  PORT MAP (
109  mac_clk => mac_clk,
110  rst_macclk => rst_macclk,
111  mac_rx_data => mac_rx_data,
112  mac_rx_error => mac_rx_error,
113  mac_rx_last => mac_rx_last,
114  mac_rx_valid => mac_rx_valid,
115  Got_IP_addr => Remote_Got_IP_addr,
116  mac_tx_ready => mac_tx_ready,
117  mac_tx_data => mac_tx_data,
118  mac_tx_error => mac_tx_error,
119  mac_tx_last => mac_tx_last,
120  mac_tx_valid => mac_tx_valid,
121  node_rx_data => slave_rx_data,
122  node_rx_err => node_rx_err,
123  node_tx_pause => master_tx_pause,
124  node_tx_data => slave_tx_data
125  );
126 
127  U_1 : entity work.interconnect
128  PORT MAP (
129  mac_clk => mac_clk,
132  tx_data => slave_tx_data,
133  master_rx_err => slave_rx_err,
135  rx_data => slave_rx_data
136  );
137  U_2 :entity ipbus_lib.ipbus_ctrl
138  GENERIC MAP (
139  MAC_CFG => EXTERNAL,
140  IP_CFG => EXTERNAL,
141  -- Number of address bits to select RX or TX buffer in UDP I/F
142  -- Number of RX and TX buffers is 2**BUFWIDTH
143  BUFWIDTH => 4,
144  -- Numer of address bits to select internal buffer in UDP I/F
145  -- Number of internal buffers is 2**INTERNALWIDTH
146  INTERNALWIDTH => 1,
147  -- Number of address bits within each buffer in UDP I/F
148  -- Size of each buffer is 2**ADDRWIDTH
149  ADDRWIDTH => 11,
150  -- Flag whether this UDP I/F instance ignores everything except IPBus traffic
151  SECONDARYPORT => '1',
152  -- Switch between using DHCP or RARP as the protocol for external IP address management
153  -- '0' => RARP, '1' => DHCP
154  DHCP_RARP => '0',
155  N_OOB => 0
156  )
157  PORT MAP (
158  mac_clk => mac_clk,
159  rst_macclk => rst_macclk,
160  ipb_clk => ipb_clk,
161  rst_ipb => rst_ipb,
162  mac_rx_data => mac_rx_data,
163  mac_rx_valid => mac_rx_valid,
164  mac_rx_last => mac_rx_last,
165  mac_rx_error => mac_rx_error,
166  mac_tx_data => mac_tx_data,
167  mac_tx_valid => mac_tx_valid,
168  mac_tx_last => mac_tx_last,
169  mac_tx_error => mac_tx_error,
170  mac_tx_ready => mac_tx_ready,
171  ipb_out => ipb_out,
172  ipb_in => ipb_in,
173  ipb_req => OPEN,
174  ipb_grant => ipb_grant,
175  mac_addr => MAC_addr,
176  ip_addr => IP_addr,
177  ipbus_port => IPBUSPORT, -- UDP port for IPbus traffic in this instance of UDP I/F
178  enable => enable,
179  ipam_select => RARP,
180  actual_mac_addr => actual_mac_addr,
181  actual_ip_addr => actual_ip_addr,
182  Got_IP_addr => Remote_Got_IP_addr,
183  pkt => OPEN
184 
185  );
186 END Behavioral;
Top ipbus interconnection.
out rx_data std_logic_vector( 8 DOWNTO 0)
slave_rx_data
in mac_clk std_logic
clock 125 MHz
in master_rx_data std_logic_vector( 9 DOWNTO 0)
IPBUS signals of master rx_data from control FPGA.
in tx_data std_logic_vector( 8 DOWNTO 0)
slave_tx_data
out master_rx_err std_logic
parity error
in rst_macclk std_logic
macclk Reset input
out process_tx_data std_logic_vector( 9 DOWNTO 0)
master_tx_data
process FPGA ipbus connection
process FPGA ipbus connection
in master_tx_pause std_logic
IPBUS signals of master_tx_pause from control FPGA.
out ipb_out ipb_wbus
IPBus output bus going from slaves to master.
in ipb_in ipb_rbus
IPBus input bus going from master to slaves.
in mac_clk std_logic
clock 125 MHz
in force_rx_error std_logic
Disable incoming rx_data from control FPGA.
in master_rx_data std_logic_vector( 9 DOWNTO 0)
IPBUS signals of master rx_data from control FPGA.
in rst_ipb std_logic
IPBus Reset input.
out master_tx_data std_logic_vector( 9 DOWNTO 0)
IPBUS signals of master tx_data to control FPGA.
in ipb_clk std_logic
IPBus clock of 31.25MHz.
in rst_macclk std_logic
macclk Reset input