process FPGA ipbus connection
This is the top level of the IPBUS control to the proccess FPGAs. There are 3 sections in this block: 1.udp slave if .
- Inter FPGA protocol is as follows:
- A frame is defined from first valid data until last is asserted (i.e. no explicit BOF)
- Format of the data between the FPGA is 8 bit data & 1 bit valid
- Valid set to 1 implies valid data, valid set to 0 that the data are a K character as below
- Valid data are put into a FIFO and if a K character is sent the next tick then this is
- used to assert last and error (corresponding to tuser in the AXI MAC) as follows:
- K28.0 => last
- K28.2 => last and error
- If err is asserted during a frame error is automatically asserted at the end of the frame
- Idle is indicated by K28.1 and K28.5
- By default K28.5 is used, but in the direction from slave to master K28.1 is used to signify
- Got_IP_addr set to 0
- N.B. assumption is that no other K chars are used so tests on K chars are not exhaustive
- HGFEDCBA
- K28.0 "00011100"
- K28.1 "00111100"
- K28.2 "01011100"
- K28.5 "10111100" This version selects the addressed slave depending on the state of incoming control lines.
2.Interconnectins of master rx and master tx to the control .
- This block generates even parity of the data and adds to tx data.
- It also performs parity check to the rx data from the control FPGA
3.Ipbus cntrl.
- This is top level of the ipbus bus master
- it bridges ethernet MAC interface and / or out-of-band interfaces to the ipbus
- Author
- Mohammed Siyad
Definition in file Process_FPGA_IPbus.vhd.
1.9.1