Behavioral Architecture Reference

process FPGA ipbus connection More...

Signals
actual_ip_addr	std_logic_vector ( 31 DOWNTO 0 )
actual_mac_addr	std_logic_vector ( 47 DOWNTO 0 )
IP_addr	std_logic_vector ( 31 DOWNTO 0 )
MAC_addr	std_logic_vector ( 47 DOWNTO 0 )
RARP	std_logic
Remote_Got_IP_addr	std_logic
enable	std_logic
ipb_grant	std_logic := ' 1 '
mac_rx_data	std_logic_vector ( 7 DOWNTO 0 )
mac_rx_error	std_logic
mac_rx_last	std_logic
mac_rx_valid	std_logic
slave_rx_data	std_logic_vector ( 8 DOWNTO 0 )
slave_rx_err	std_logic
node_rx_err	std_logic
mac_tx_data	std_logic_vector ( 7 DOWNTO 0 )
mac_tx_error	std_logic
mac_tx_last	std_logic
mac_tx_ready	std_logic
mac_tx_valid	std_logic
slave_tx_data	std_logic_vector ( 8 DOWNTO 0 )

Instantiations
u_0	udp_node_if
u_1	interconnect <Entity interconnect>
u_2	ipbus_ctrl

Detailed Description

process FPGA ipbus connection

This is the top level of the IPBUS control to the proccess FPGAs. There are 3 sections in this block: 1.udp slave if .

• Inter FPGA protocol is as follows:
• A frame is defined from first valid data until last is asserted (i.e. no explicit BOF)
• Format of the data between the FPGA is 8 bit data & 1 bit valid
• Valid set to 1 implies valid data, valid set to 0 that the data are a K character as below
• Valid data are put into a FIFO and if a K character is sent the next tick then this is
• used to assert last and error (corresponding to tuser in the AXI MAC) as follows:
• K28.0 => last
• K28.2 => last and error
• If err is asserted during a frame error is automatically asserted at the end of the frame
• Idle is indicated by K28.1 and K28.5
• By default K28.5 is used, but in the direction from slave to master K28.1 is used to signify
• Got_IP_addr set to 0
• N.B. assumption is that no other K chars are used so tests on K chars are not exhaustive
• HGFEDCBA
• K28.0 "00011100"
• K28.1 "00111100"
• K28.2 "01011100"
• K28.5 "10111100" This version selects the addressed slave depending on the state of incoming control lines.

2.Interconnectins of master rx and master tx to the control .

• This block generates even parity of the data and adds to tx data.
• It also performs parity check to the rx data from the control FPGA

3.Ipbus cntrl.

• This is top level of the ipbus bus master
• it bridges ethernet MAC interface and / or out-of-band interfaces to the ipbus

Author

Mohammed Siyad

Definition at line 74 of file Process_FPGA_IPbus.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/Process_FPGA_IPbus.vhd