interconnect Entity Reference

Top ipbus interconnection. More...

Inheritance diagram for interconnect:

Entities
struct	architecture
	Top ipbus interconnection. More...

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith

Ports
mac_clk	in	std_logic
		clock 125 MHz
master_rx_data	in	std_logic_vector ( 9 DOWNTO 0 )
		IPBUS signals of master rx_data from control FPGA.
rst_macclk	in	std_logic
		macclk Reset input
tx_data	in	std_logic_vector ( 8 DOWNTO 0 )
		slave_tx_data
master_rx_err	out	std_logic
		parity error
process_tx_data	out	std_logic_vector ( 9 DOWNTO 0 )
		master_tx_data
rx_data	out	std_logic_vector ( 8 DOWNTO 0 )
		slave_rx_data

Detailed Description

Top ipbus interconnection.

This block interconnects between the process FPGA master rx and master tx to the control FPGA. It generates even parity of the tx data and adds to tx data. It also performs parity check to the rx data from the control FPGA

Author

Mohammed Siyad

Definition at line 15 of file interconnect_struct.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd