struct Architecture Reference

Top ipbus interconnection. More...

Processes
PROCESS_60	( mac_clk )

Signals
master_rx_data_int	std_logic_vector ( 9 downto 0 )
process_tx_data_int	std_logic_vector ( 9 downto 0 )

Instantiations
u_1	parity_checker <Entity parity_checker>
u_0	parity_gen <Entity parity_gen>

Detailed Description

Top ipbus interconnection.

This block interconnects between the process FPGA master rx and master tx to the control FPGA. It generates even parity of the tx data and adds to tx data. It also performs parity check to the rx data from the control FPGA

Author

Mohammed Siyad

Definition at line 36 of file interconnect_struct.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd