parity_gen Entity Reference

parity genrator More...

Inheritance diagram for parity_gen:

Entities
spec	architecture
	parity genrator More...

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith

Generics
width	integer := 9

Ports
CLK	in	std_logic
		clock 125 MHz
Data_in	in	std_logic_vector ( width- 1 downto 0 )
		data in to the parity generator block
data_Parity	out	std_logic_vector ( width downto 0 )
		data with parity

Detailed Description

parity genrator

It generates even parity of the tx data and adds to tx data.

Author

Mohammed Siyad

Definition at line 12 of file parity_gen_spec.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd