parity_gen_spec.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY parity_gen IS
 
  Generic( width :integer:= 9);
    PORT
     (
        CLK     :IN std_logic;    
        Data_in :IN std_logic_vector(width-1 downto 0);
        data_Parity  :OUT std_logic_vector(width downto 0)
        );
          
END ENTITY parity_gen;
 
ARCHITECTURE spec OF parity_gen IS
 
BEGIN
  
odd_parity: Process(clk)
        
variable temp: std_logic:='0';   
     
            Begin
             
                 
                 if CLK' event and CLK ='1' then                               
                    temp :=  '0';  
                            
                   for i in 0 to width-1 loop
                     
                     temp := temp xor data_in(i);
                                          
                   end loop;                
                                   
                  data_parity <= (temp & data_in);
                  
                   end if; 
                                           
              end process;
              
             
                   
END ARCHITECTURE spec;