eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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Inter_Connection Directory Reference

Files

file  bcn_l1a_valid_checker.vhd [code]
 Observes BCN ID, L1A ID, and parity bits.
 
file  interconnect_struct.vhd [code]
 Top ipbus interconnection.
 
file  parity_checker_spec.vhd [code]
 parity checker
 
file  parity_gen_spec.vhd [code]
 parity genrator
 
file  Process_FPGA_IPbus.vhd [code]
 process FPGA ipbus connection
 
file  ttc_parity.vhd [code]
 generate parity for data going from Control FPGA to Processors