ttc_parity.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY ttc_parity IS
GENERIC (
    SEED: STD_LOGIC := '1'); -- default is odd parity
PORT (
    ttc_data: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    parity12: OUT STD_LOGIC;
    parity32: OUT STD_LOGIC);
END ttc_parity;
 
ARCHITECTURE rtl OF ttc_parity IS
    SIGNAL parity_calc: STD_LOGIC_VECTOR(31 DOWNTO 0);
    SIGNAL parity_merge: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
 
-- Generate even parity over each individual nibble
    parity_nibble: for j in 0 to 7 generate
        parity_calc(j*4) <= ttc_data(j*4);
        parity_bit: for i in 1 to 3 generate
            parity_calc((j*4)+i) <= parity_calc((j*4)+i-1) XOR ttc_data((j*4)+i);
        end generate parity_bit;
    end generate parity_nibble;
 
-- Merge nibble parities (even/odd based on SEED)
    parity_merge(0) <= parity_calc(3) XOR SEED;
    parity_accumulate: for j in 1 to 7 generate
        parity_merge(j) <= parity_calc((j*4)+3) XOR parity_merge(j-1);
    end generate parity_accumulate;
 
    parity12 <= parity_merge(2); -- BCN
    parity32 <= parity_merge(7); -- L1ID
 
END rtl;